;	TITLE	BMP.bsf - BMP Script File for Video BIOS
;==============================================================================
; Advance Graphics ROM BIOS
;------------------------------------------------------------------------------
; Copyright (c) Intel Corporation (2000 - 2011).
;
; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS
; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT,
; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES.
; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS.
; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY,
; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER
; WARRANTY.
;
; Intel disclaims all liability, including liability for infringement of
; any proprietary rights, relating to use of the code. No license, express
; or implied, by estoppel or otherwise, to any intellectual property rights
; is granted herein.
;
; File Description:
;	This file is the script file use by the BMP utility which will allow
;	OEM's to edit data and select features on a binary file.
;
;------------------------------------------------------------------------------

;==============================================================================
; Header - Start of BMP Structure Definition
;------------------------------------------------------------------------------

StructDef

Find			"BIOS_DATA_BLOCK "

			; The following block will determine the reference
			; pointer for all table pointer variables.

Find_Ptr_Ref		"BIOS_DATA_BLOCK" ; Reference to beginning of VB VBT data

$BDB_Ver		2 bytes		; BIOS Data Block version number (decimal, e.g.201 = 02.01) 
$BDB_Header_Size	2 bytes		; BIOS Data Block Header size
$BDB_Size		2 bytes		; BIOS Data Block size 

;==============================================================================
; Block 254 - Signon Strings and Other General Data
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$Bmp_BIOS_Size		2 bytes
$BIOS_Type		1 byte		; BIOS Type:
					; = 0, DESKTOP
					; = 1, MOBILE

$RelStage		1 byte		; Release status

$Chipset		1 byte		; = 17 - SandyBridge-Desktop  
					; = 18 - Sandybridge-Mobile				
					; = 19 - Ivybridge-Desktop				
					; = 20 - Ivybridge-Mobile				
					; = 21 - Haswell				
					; = 22 - Broadwell
									

$Integrated_LVDS	1 bit		; Integrated LVDS Support:
					; 1 = Yes
					; 0 = None

$Integrated_TV		1 bit		; Integrated TV Support:
					; 1 = Yes
					; 0 = None

$Integrated_EFP		1 bit		; Integrated EFP Support:
					; 1 = Yes
					; 0 = None

$eDP			1 bit		; eDP:
					; 1 = Yes
					; 0 = None

SKIP			4 bits
SKIP			4 bytes		; Skip build number string

			; Signon and copyright strings

$Signon			155 bytes	; Signon string
$Copyright		61 bytes	; Copyright string

			; General Byte Definitions

$bmp_BIOS_CS		2 bytes		; BIOS code segment
$bmp_VBIOS_Post_Mode	1 byte		; Mode number to set during V BIOS POST
$bmp_BW_Percent		1 byte		; Set percentage of total memory BW
SKIP			1 byte		; Popup Memory Size
$bmp_Resize_PCI_BIOS	1 byte		; BIOS size granularity in 0.5 KB
SKIP			1 byte		; Is the CRT already switched to DDC2

$Allow_Boot_DVI		1 bit		; Allow boot DVI even not attach
$Allow_Aspect_Ratio	1 bit		; VBIOS aspect ratio for DOS
SKIP			6 bits

ALIGN

;==============================================================================
; Block 1 - General Bit Definitions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

			; bmp_Bits_1

$Enable_Panel_Fitting	2 bits		; Enable / Disable panel fitting
$Flexaim_Support	1 bit		; Enable / Disable Flex-aim support
$Msg_Enable		1 bit		; Disable signon and copyright
$Cls_After_Signon	3 bits		; Clear screen after display message and pause
$bmp_DVO_A_Color_Flip	1 bit		; Flat color flip
ALIGN

			; bmp_Bits_2

$Download_Ext_VBT 	1 bit		; Download external VBT flag
$Enable_SSC		1 bit		; Enable/Disable SSC
$SSC_Freq		1 bit		; SSC Frequency
$Enable_LFPOn_Override	1 bit		; Enable/Disable LFP ON Override
$Disable_SSC_DDT	1 bit		; Disable SSC in Dual Display Twin
$Override_VGA_720p	1 bit		; Enable/Disable Override 720p for VGA modes
$bmp_Dynamic_CdClock_Supported  1 bit ; Enable/Disable Dynamic CD Clock select
$Hotplug_Support_Enb	1 bit		; Hot Plug support in DOS

ALIGN

			; bmp_Bits_3

$Disable_Smooth_Vision	1 bit		; Reserved/Obolete
$Single_DVI_I		1 bit		; Single DVI-I connector for CRT and DVI display
SKIP			1 bit		; Reserved/Obolete
$FDI_RX_POL		1 bit		; FDI Rx Polarity Normal/Inverted
$Extd_DT_Mode		1 bit		; DUAL mode bit
$Copy_DTD		1 bit		; Copy iLFP DTD to sDVO DTD
$Enable_Panel_Timing	1 bit		; Enable / Disable panel fitting
SKIP	 		1 bit		; Reserved
ALIGN

$bmp_Legacy_Monitor_Detect  1 bit	; Reserved/Obolete
SKIP			7 bits
ALIGN

			; Int_Displays_Support

$Int_CRT_Support	1 bit		; Integrated CRT support
$Int_TV_Support		1 bit		; Integrated TV support
$Int_EFP_Support	1 bit		; Integrated EFP support
$DP_SSC_Enb		1 bit		; DP SSC Enable bit
$DP_SSC_Freq		1 bit		; DP SSC Frequency bit
$DP_SSC_Dongle_Enb	1 bit		; DP SSC dongle Enable/Disable
SKIP			2 bits		; Reserved

ALIGN

;==============================================================================
; Block 253 - PRD Boot Algorithm Table
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP                        1 byte
$ChildDevice1Primary        1 byte
$ChildDevice1Secondary      1 byte
SKIP                        1 byte
$ChildDevice2Primary        1 byte
$ChildDevice2Secondary      1 byte
SKIP                        1 byte
$ChildDevice3Primary        1 byte
$ChildDevice3Secondary      1 byte
SKIP                        1 byte
$ChildDevice4Primary        1 byte
$ChildDevice4Secondary      1 byte
SKIP                        1 byte
$ChildDevice5Primary        1 byte
$ChildDevice5Secondary      1 byte
SKIP                        1 byte
$ChildDevice6Primary        1 byte
$ChildDevice6Secondary      1 byte
SKIP                        1 byte
$ChildDevice7Primary        1 byte
$ChildDevice7Secondary      1 byte
SKIP                        1 byte
$ChildDevice8Primary        1 byte
$ChildDevice8Secondary      1 byte
SKIP                        1 byte
$ChildDevice9Primary        1 byte
$ChildDevice9Secondary      1 byte
SKIP                        1 byte
$ChildDevice10Primary       1 byte
$ChildDevice10Secondary     1 byte
SKIP                        1 byte
$ChildDevice11Primary       1 byte
$ChildDevice11Secondary     1 byte
SKIP                        1 byte
$ChildDevice12Primary       1 byte
$ChildDevice12Secondary     1 byte
SKIP                        1 byte
$ChildDevice13Primary       1 byte
$ChildDevice13Secondary     1 byte
SKIP                        1 byte
$ChildDevice14Primary       1 byte
$ChildDevice14Secondary     1 byte
SKIP                        1 byte
$ChildDevice15Primary       1 byte
$ChildDevice15Secondary     1 byte
SKIP                        1 byte
$ChildDevice16Primary       1 byte
$ChildDevice16Secondary     1 byte

SKIP                        2 bytes        ; No of entries

;==============================================================================
; Block 2 - General Data Definitions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

			; bmp_DDC_GPIO_Pins

$CRT_DDC_GMBUS_Pin	1 byte		; CRT DDC GMBUS pin pair

			; bmp_DPMS_Bits

$DPMS_ACPI_Bit		1 bit		; Apply ACPI DPMS CRT Power States
$Skip_Boot_CRT_Detect	1 bit		; Disable/Enable skip boot CRT detect
$DPMS_AIM_Bit		1 bit		; Apply DPMS to AIM devices
SKIP			5 bits		; Reserved
ALIGN

			; bmp_Boot_Dev_Bits

$Boot_Display		2 bytes		; Boot display type

$size_ChildStruc	1 byte

			; Internal LVDS Data structure

#IF	$Integrated_LVDS == 1 || $eDP == 1
  SKIP			16 bytes	; Skip till eDP port select
  $Int_eDP_Port		1 byte		; eDP port select
  SKIP			2 bytes		; Skip remaining Data structure
  $LFP_DDC_GMBUS_Pin	1 byte		; LFP DDC GMBUS pin pair	
  SKIP 3 bytes
  SKIP          1 bit
  $LFP_Lane_Reversal			    1 bit		; Port Reversal
  SKIP					6 bits		; Reserved
  SKIP 1 byte
  $Int_LFP_AUX_Channel  1 byte		; eDP AUX channel
  SKIP			7 bytes	; Skip remaining Data structure
#ENDIF	; $Integrated_LVDS || $eDP

			; Internal EFP (HDMI/DP) Data structure

			; Device 1

SKIP					2 bytes		; Skip Device Handle
$Int_EFP1_Type	2 bytes					; Device type
SKIP					1 byte		; I2C Speed
$Int_EFP1_OnBoard_Pre_emphasis		3 bits		; Set DisplayPort Pre-Emphasis level for onboard Redriver
$Int_EFP1_OnBoard_Voltage_Swing		3 bits		; Set DisplayPort Voltage Swing level for onboard Redriver
$Int_EFP1_OnBoard_Redriver_Present	1 bit		; Set if onboard Redriver is present
SKIP					1 bit		; Reserved
ALIGN
$Int_EFP1_Dock_Pre_emphasis		3 bits		; Set DisplayPort Redriver Pre-Emphasis level for dock Redriver
$Int_EFP1_Dock_Voltage_Swing		3 bits		; Set DisplayPort Redriver Voltage Swing level for dock Redriver
$Int_EFP1_Dock_Redriver_Present		1 bit		; Set if dock Redriver is present
SKIP					1 bit		; Reserved
ALIGN
$Int_EFP1_HDMI_LS_Type			5 bits		; HDMI Level shifter configuration
SKIP					3 bits		; Reserved
ALIGN
SKIP					2 bytes		; Skip EDIDless DTD offset
$EFP1_EDIDless_en			1 bit		; EDIDless enable bit
SKIP					7 bits		; Skip remaining bits
SKIP					3 bytes		; Skip Reserved_1
SKIP					2 bytes		; skip Addin module table offset
$Int_EFP1_Port				1 byte		; EFP1 port
SKIP					2 bytes		; Skip
$Int_EFP1_DDC_Pin			1 byte		; EFP1 DDC Pin
SKIP					3 bytes
$Int_EFP1_Port_Dockable			1 bit		; HDMI/DP Docked Port
$EFP1_Lane_Reversal			    1 bit		; Port Reversal
SKIP					6 bits		; Reserved
ALIGN
;$Int_EFP1_HDMI_Compat			1 bit		; HDMI combatibility
;$Int_EFP1_Conn_Info			3 bits		; Connector information
;SKIP					4 bits
$Int_EFP1_Type_Compat   1 byte          ; EFP compatibility field
$Int_EFP1_AUX_Channel			1 byte		; DP AUX channel
$Int_EFP1_Dongle_Detect 		1 byte          ; Dongle Detect
SKIP					6 bytes		; Skip

			; Device 2

SKIP					2 bytes		; Skip Device Handle
$Int_EFP2_Type	2 bytes					; Device type
SKIP					1 byte		; I2C Speed
$Int_EFP2_OnBoard_Pre_emphasis		3 bits		; Set DisplayPort Pre-Emphasis level for onboard Redriver
$Int_EFP2_OnBoard_Voltage_Swing		3 bits		; Set DisplayPort Voltage Swing level for onboard Redriver
$Int_EFP2_OnBoard_Redriver_Present	1 bit		; Set if onboard Redriver is present
SKIP					1 bit		; Reserved
ALIGN
$Int_EFP2_Dock_Pre_emphasis		3 bits		; Set DisplayPort Redriver Pre-Emphasis level for dock Redriver
$Int_EFP2_Dock_Voltage_Swing		3 bits		; Set DisplayPort Redriver Voltage Swing level for dock Redriver
$Int_EFP2_Dock_Redriver_Present		1 bit		; Set if dock Redriver is present
SKIP					1 bit		; Reserved
ALIGN
$Int_EFP2_HDMI_LS_Type			5 bits		; HDMI Level shifter configuration
SKIP					3 bits		; Reserved
ALIGN
SKIP					2 bytes		; Skip EDIDless DTD offset
$EFP2_EDIDless_en			1 bit		; EDIDless enable bit
SKIP					7 bits		; Skip remaining bits
SKIP					3 bytes		; Skip Reserved_1
SKIP					2 bytes		; skip Addin module table offset
$Int_EFP2_Port				1 byte		; EFP1 port
SKIP					2 bytes		; Skip
$Int_EFP2_DDC_Pin			1 byte		; EFP1 DDC Pin
SKIP					3 bytes
$Int_EFP2_Port_Dockable			1 bit		; HDMI/DP Docked Port
$EFP2_Lane_Reversal			    1 bit		; Port Reversal
SKIP					6 bits		; Reserved

ALIGN
;$Int_EFP2_HDMI_Compat			1 bit		; HDMI combatibility
;$Int_EFP2_Conn_Info			3 bits		; Connector information
;SKIP					4 bits
$Int_EFP2_Type_Compat   1 byte          ; EFP compatibility field
$Int_EFP2_AUX_Channel			1 byte		; DP AUX channel
$Int_EFP2_Dongle_Detect 		1 byte          ; Dongle Detect
SKIP					6 bytes		; Skip

			; Device 3

SKIP					2 bytes		; Skip Device Handle
$Int_EFP3_Type	2 bytes					; Device type
SKIP					1 byte		; I2C Speed
$Int_EFP3_OnBoard_Pre_emphasis		3 bits		; Set DisplayPort Pre-Emphasis level for onboard Redriver
$Int_EFP3_OnBoard_Voltage_Swing		3 bits		; Set DisplayPort Voltage Swing level for onboard Redriver
$Int_EFP3_OnBoard_Redriver_Present	1 bit		; Set if onboard Redriver is present
SKIP					1 bit		; Reserved
ALIGN
$Int_EFP3_Dock_Pre_emphasis		3 bits		; Set DisplayPort Redriver Pre-Emphasis level for dock Redriver
$Int_EFP3_Dock_Voltage_Swing		3 bits		; Set DisplayPort Redriver Voltage Swing level for dock Redriver
$Int_EFP3_Dock_Redriver_Present		1 bit		; Set if dock Redriver is present
SKIP					1 bit		; Reserved
ALIGN
$Int_EFP3_HDMI_LS_Type			5 bits		; HDMI Level shifter configuration
SKIP					3 bits		; Reserved
ALIGN
SKIP					2 bytes		; Skip EDIDless DTD offset
$EFP3_EDIDless_en			1 bit		; EDIDless enable bit
SKIP					7 bits		; Skip remaining bits
SKIP					3 bytes		; Skip Reserved_1
SKIP					2 bytes		; skip Addin module table offset
$Int_EFP3_Port				1 byte		; EFP1 port
SKIP					2 bytes		; Skip
$Int_EFP3_DDC_Pin			1 byte		; EFP1 DDC Pin
SKIP					3 bytes
$Int_EFP3_Port_Dockable			1 bit		; HDMI/DP Docked Port
$EFP3_Lane_Reversal			    1 bit		; Port Reversal
SKIP					6 bits		; Reserved

ALIGN
;$Int_EFP3_HDMI_Compat			1 bit		; HDMI combatibility
;$Int_EFP3_Conn_Info			3 bits		; Connector information
;SKIP					4 bits
$Int_EFP3_Type_Compat   1 byte          ; EFP compatibility field
$Int_EFP3_AUX_Channel			1 byte		; DP AUX channel
$Int_EFP3_Dongle_Detect 		1 byte          ; Dongle Detect
SKIP					6 bytes		; Skip

SKIP			33 bytes	; Skip device data structure
SKIP			33 bytes	; Skip device data structure
SKIP			33 bytes	; Skip device data structure
SKIP			33 bytes	; Skip device data structure

;==============================================================================
; Block 3 - Original Display Toggle List
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$bmp_Display_Detect	1 byte		; Display must be attached or not

;==============================================================================
; Block 4 - Mode Support Bit Definitions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			28 bytes	; Mode List

;==============================================================================
; Block 252 - Hook Defintions
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$H31_POST_End_Hook	1 byte		; POST end hook int vector
$H33_After_Mode_Set	1 byte		; After mode set hook
$H35_Bootup_Display	1 byte		; Bootup display hook
$H38_Before_Mode_Set	1 byte		; Before mode set hook
$H45_VESA_DDC_Hook	1 byte		; VESA DDC hook interrupt vector
$H46_VESA_PM_Hook	1 byte		; VESA PM hook interrupt vector
$H47_Notify_Display_Sw	1 byte		; Notify display switch hook
$H48_After_VESA_PM	1 byte		; After VESA PM hook
$H14_Update_Display	1 byte		; Update Expansion/Display State Hook
$H14_Get_Misc_Status	1 byte		; Get Miscellaneous Status Hook
$H36_Boot_TV_Format	1 byte		; Boot TV to NTSC/PAL
$H34_Set_LFP_Fitting	1 byte		; Set panel fitting flags
$H40_Set_Panel_Type	1 byte		; Set panel fitting flags
$H49_Get_BL_Inv_Pol     1 byte		; Get inverter type and polarity for backlight
$H51_LFP_Panel_Type	1 byte		; Get active LFP configuration
$H52_LFP_Panel_Color_Depth	1 byte
$H53_Get_EDID_SBIOS	1 byte		; Hook to get EDID from system BIOS
$H54_Get_Int_DP_HDMI_Cfg	1 byte		; Hook to get Integrated DP/HDMI port configuration      

			; BMP - Pointer tables

$Dev_Boot_Table_Ptr	2 bytes		; Start at BMP Boot table
$Dev_Boot_Table_Size	2 bytes
$Dev_Boot_Table,	$Dev_Boot_Table_Ptr, $Dev_Boot_Table_Size, Offset 0 byte

$Dev_Removed_Table_Ptr	2 bytes		; Start at BMP Remove configurations table
$Dev_Removed_Table_Size	2 bytes
$Dev_Removed_Table,	$Dev_Removed_Table_Ptr, $Dev_Removed_Table_Size, Offset 0 byte

$MMIO_Boot_Table_Ptr	2 bytes		; Start at BMP Boot table
$MMIO_Boot_Table_Size	2 bytes
$MMIO_Boot_Table,	$MMIO_Boot_Table_Ptr, $MMIO_Boot_Table_Size, Offset 0 byte

$SWF_IO_Table_Ptr	2 bytes
$SWF_IO_Table_Size	2 bytes
$SWF_IO_Table,		$SWF_IO_Table_Ptr, $SWF_IO_Table_Size, Offset 3 bytes

$SWF_MMIO_Table_Ptr	2 bytes
$SWF_MMIO_Table_Size	2 bytes
$SWF_MMIO_Table,	$SWF_MMIO_Table_Ptr, $SWF_MMIO_Table_Size, Offset 3 bytes

$Mode_Rem_Table_Ptr	2 bytes		; Start at BMP Boot table
$Mode_Rem_Table_Size	2 bytes
$Mode_Rem_Table,	$Mode_Rem_Table_Ptr, $Mode_Rem_Table_Size, Offset 0 byte

$Toggle_List1_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List1_Size	2 bytes
$Toggle_List1,		$Toggle_List1_Ptr, $Toggle_List1_Size, Offset 0 byte

$Toggle_List2_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List2_Size	2 bytes
$Toggle_List2,		$Toggle_List2_Ptr, $Toggle_List2_Size, Offset 0 byte

$Toggle_List3_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List3_Size	2 bytes
$Toggle_List3,		$Toggle_List3_Ptr, $Toggle_List3_Size, Offset 0 byte

$Toggle_List4_Ptr	2 bytes		; Start at BMP Boot table
$Toggle_List4_Size	2 bytes
$Toggle_List4,		$Toggle_List4_Ptr, $Toggle_List4_Size, Offset 0 byte

$ScalarCoeff_Tab_Ptr	2 bytes
$ScalarCoeff_Tab_Size	2 bytes
$ScalarCoeff_Tab,	$ScalarCoeff_Tab_Ptr, $ScalarCoeff_Tab_Size, Offset 0 bytes

$LFP_DTD_01_Ptr		2 bytes
$LFP_DTD_01_Size	2 bytes
$LFP_DTD_01,		$LFP_DTD_01_Ptr, $LFP_DTD_01_Size, Offset 0 bytes
$LFP_DTD_02_Ptr		2 bytes
$LFP_DTD_02_Size	2 bytes
$LFP_DTD_02,		$LFP_DTD_02_Ptr, $LFP_DTD_02_Size, Offset 0 bytes
$LFP_DTD_03_Ptr		2 bytes
$LFP_DTD_03_Size	2 bytes
$LFP_DTD_03,		$LFP_DTD_03_Ptr, $LFP_DTD_03_Size, Offset 0 bytes
$LFP_DTD_04_Ptr		2 bytes
$LFP_DTD_04_Size	2 bytes
$LFP_DTD_04,		$LFP_DTD_04_Ptr, $LFP_DTD_04_Size, Offset 0 bytes

$LFP_PID_01_Ptr		2 bytes
$LFP_PID_01_Size	2 bytes
$LFP_PID_01,		$LFP_PID_01_Ptr, $LFP_PID_01_Size, Offset 0 bytes
$LFP_PID_02_Ptr		2 bytes
$LFP_PID_02_Size	2 bytes
$LFP_PID_02,		$LFP_PID_02_Ptr, $LFP_PID_02_Size, Offset 0 bytes
$LFP_PID_03_Ptr		2 bytes
$LFP_PID_03_Size	2 bytes
$LFP_PID_03,		$LFP_PID_03_Ptr, $LFP_PID_03_Size, Offset 0 bytes
$LFP_PID_04_Ptr		2 bytes
$LFP_PID_04_Size	2 bytes
$LFP_PID_04,		$LFP_PID_04_Ptr, $LFP_PID_04_Size, Offset 0 bytes

$LFP_Pwr_Seq_01_Ptr	2 bytes
$LFP_Pwr_Seq_01_Size	2 bytes
$LFP_Pwr_Seq_01,	$LFP_Pwr_Seq_01_Ptr, $LFP_Pwr_Seq_01_Size, Offset 0 bytes
$LFP_Pwr_Seq_02_Ptr	2 bytes
$LFP_Pwr_Seq_02_Size	2 bytes
$LFP_Pwr_Seq_02,	$LFP_Pwr_Seq_02_Ptr, $LFP_Pwr_Seq_02_Size, Offset 0 bytes
$LFP_Pwr_Seq_03_Ptr	2 bytes
$LFP_Pwr_Seq_03_Size	2 bytes
$LFP_Pwr_Seq_03,	$LFP_Pwr_Seq_03_Ptr, $LFP_Pwr_Seq_03_Size, Offset 0 bytes
$LFP_Pwr_Seq_04_Ptr	2 bytes
$LFP_Pwr_Seq_04_Size	2 bytes
$LFP_Pwr_Seq_04,	$LFP_Pwr_Seq_04_Ptr, $LFP_Pwr_Seq_04_Size, Offset 0 bytes

#IF	$eDP == 1		; $eDP == TRUE
  SKIP			64 bytes	; Skip data 
#ENDIF	; $eDP == 1		; $eDP == TRUE

;==============================================================================
; Block 6 - Extended MMIO Register tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			117 bytes	; Skip data 

;==============================================================================
; Block 7 - IO Software flag register table for initializaton
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			7 bytes		; Skip data

;==============================================================================
; Block 8 - MMIO Software flag register table for initializaton
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			61 bytes	; Skip data

;==============================================================================
; Block 9 - PSR/SRD feature control block
;------------------------------------------------------------------------------

SKIP				3 bytes		; Skip block ID and size

	; Panel #1

$PSR_FullLink_Enable_01		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_01	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_01		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_01	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved
ALIGN

$PSR_TP1_WaitTime_01		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_01		2 bytes			; TP2/TP3 wake up time in multiples of 100
ALIGN
	; Panel #2

$PSR_FullLink_Enable_02		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_02	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_02		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_02	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_02		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_02		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #3

$PSR_FullLink_Enable_03		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_03	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_03		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_03	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_03		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_03		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #4

$PSR_FullLink_Enable_04		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_04	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved

 
$PSR_IdleFrames2Wait_04		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_04	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_04		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_04		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #5

$PSR_FullLink_Enable_05		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_05	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_05		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_05	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_05		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_05		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #6

$PSR_FullLink_Enable_06		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_06	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_06		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_06	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_06		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_06		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #7

$PSR_FullLink_Enable_07		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_07	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_07		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_07	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_07		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_07		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #8

$PSR_FullLink_Enable_08		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_08	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_08		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_08	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_08		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_08		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #9

$PSR_FullLink_Enable_09		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_09	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_09		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_09	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_09		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_09		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #10

$PSR_FullLink_Enable_10		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_10	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_10		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_10	3 bits			; Lines to wait before link standby
SKIP				1 bit

$PSR_TP1_WaitTime_10		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_10		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #11

$PSR_FullLink_Enable_11		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_11	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_11		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_11	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_11		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_11		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #12

$PSR_FullLink_Enable_12		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_12	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_12		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_12	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_12		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_12		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #13

$PSR_FullLink_Enable_13		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_13	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_13		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_13	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_13		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_13		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #14

$PSR_FullLink_Enable_14		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_14	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_14		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_14	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_14		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_14		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #15

$PSR_FullLink_Enable_15		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_15	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_15		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_15	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_15		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_15		2 bytes			; TP2/TP3 wake up time in multiples of 100

	; Panel #16

$PSR_FullLink_Enable_16		1 bit			; Full link disable
$PSR_Require_AUX2Wakeup_16	1 bit			; Require AUX to wake up
SKIP				6 bits			; Reserved
 
$PSR_IdleFrames2Wait_16		4 bits			; Idle frames to wait for PSR enable
$PSR_Lines2Wait_B4LinkS3_16	3 bits			; Lines to wait before link standby
SKIP				1 bit			; Reserved

$PSR_TP1_WaitTime_16		2 bytes			; TP1 wake up time in multiples of 100
$PSR_TP_2_3_WaitTime_16		2 bytes			; TP2/TP3 wake up time in multiples of 100

;==============================================================================
; Block 10 - Modes Removal Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			203 bytes	; Skip data

;==============================================================================
; Block 11 - Child Device Configuration Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			1 byte		; Child structure size

			; Generic device 1 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev1_Type		2 bytes		; Device type
$Dev1_I2CSpeed		1 bytes		; I2C speed used to communicate to codec
SKIP			1 byte		; Skip on board redriver configuration
SKIP			1 byte		; Skip on dock redriver configuration
SKIP			1 byte		; Skip on HDMI configuration
SKIP			6 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev1_DVO		1 byte		; DVO port
$Dev1_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev1_Slave_Add		1 byte		; I2C slave address
$Dev1_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev1_DVO_Cfg		1 byte		; DVO Port config
$Dev1_Sec_DVO		1 byte		; DVO port
$Dev1_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev1_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev1_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev1_DVOWiring		1 byte		; DVO Wiring
$Dev1_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev1_Type_Ex		2 bytes		; Extended device class
$Dev1_DVO_Func		1 byte		; DVO function

			; Generic device 2 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev2_Type		2 bytes		; Device type
$Dev2_I2CSpeed		1 bytes		; I2C speed used to communicate to codec
SKIP			1 byte		; Skip on board redriver configuration
SKIP			1 byte		; Skip on dock redriver configuration
SKIP			1 byte		; Skip on HDMI configuration
SKIP			6 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev2_DVO		1 byte		; DVO port
$Dev2_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev2_Slave_Add		1 byte		; I2C slave address
$Dev2_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev2_DVO_Cfg		1 byte		; DVO Port config
$Dev2_Sec_DVO		1 byte		; Secondary DVO port
$Dev2_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev2_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev2_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev2_DVOWiring		1 byte		; DVO Wiring
$Dev2_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev2_Type_Ex		2 bytes		; Extended device class
$Dev2_DVO_Func		1 byte		; DVO function

			; Generic device 3 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev3_Type		2 bytes		; Device type
$Dev3_I2CSpeed		1 bytes		; I2C speed used to communicate to codec
SKIP			1 byte		; Skip on board redriver configuration
SKIP			1 byte		; Skip on dock redriver configuration
SKIP			1 byte		; Skip on HDMI configuration
SKIP			6 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev3_DVO		1 byte		; DVO port
$Dev3_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev3_Slave_Add		1 byte		; I2C slave address
$Dev3_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev3_DVO_Cfg		1 byte		; DVO Port config
$Dev3_Sec_DVO		1 byte		; Secondary DVO port
$Dev3_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev3_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev3_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev3_DVOWiring		1 byte		; DVO Wiring
$Dev3_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev3_Type_Ex		2 bytes		; Extended device class
$Dev3_DVO_Func		1 byte		; DVO function

  			; Generic device 4 data structure

SKIP			2 bytes		; Skip Device Handle
$Dev4_Type		2 bytes		; Device type
$Dev4_I2CSpeed		1 bytes		; I2C speed used to communicate to codec
SKIP			1 byte		; Skip on board redriver configuration
SKIP			1 byte		; Skip on dock redriver configuration
SKIP			1 byte		; Skip on HDMI configuration
SKIP			6 bytes		; Skip Reserved_1
SKIP			2 bytes		; Skip AddInOffset
$Dev4_DVO		1 byte		; DVO port
$Dev4_I2C_Pin		1 byte		; I2C GPIO pin pair
$Dev4_Slave_Add		1 byte		; I2C slave address
$Dev4_DDC_Pin		1 byte		; DDC GPIO pin pair
SKIP			2 bytes		; EDID Buffer Ptr
$Dev4_DVO_Cfg		1 byte		; DVO Port config
$Dev4_Sec_DVO		1 byte		; Secondary DVO port
$Dev4_Sec_I2C_Pin	1 byte		; Secondary I2C GPIO pin pair
$Dev4_Sec_Slave_Add	1 byte		; Secondary I2C slave address
$Dev4_Sec_DDC_Pin	1 byte		; Secondary DDC GPIO pin pair
SKIP			1 byte		; Capabilities
$Dev4_DVOWiring		1 byte		; DVO Wiring
$Dev4_Sec_DVOWiring	1 byte		; DVO Wiring for secondary device
$Dev4_Type_Ex		2 bytes		; Extended device class
$Dev4_DVO_Func		1 byte		; DVO function

			; ADD-Card SPD as device #6 and #7
			; They should be non-BMPable

SKIP			66 bytes	; Skip two data structures

;==============================================================================
; Block 12 - Driver default boot display
;------------------------------------------------------------------------------

SKIP		   	3 bytes		; Skip block ID and size
$Driver_Boot_Device	1 bit
$Block_Disp_Switch	1 bit
$Allow_FDOS_Disp_Switch 1 bit		; Allow FS DOS display switching
$Hot_Plug_DVO		1 bit
$Dual_View_Zoom		1 bit
$Drv_Int15_hook		1 bit
$DVD_Sprite_Clone	1 bit
$Use_110h_for_LFP	1 bit 
ALIGN

$Driver_Boot_Mode_X	2 bytes		; X resolution
$Driver_Boot_Mode_Y	2 bytes		; Y resolution
$Driver_Boot_Mode_BPP 	1 byte		; Pixel depth
$Driver_Boot_Mode_RR  	1 byte		; Refresh rate

			; bmp_Ext_Driver_Bits

$Enable_LFP_Primary	1 bit
$GTF_Mode_Pruning	1 bit
$Render_Freq_Switch	1 bit
$Render_Freq_Default	1 bit 
$NT4_Dual_Dsp_Clone_Spt 1 bit		; Dual display clone support for NT4
$Default_Power_Scheme	1 bit
$Sprite_Display_Assign	1 bit		; Sprite Display Assignment for when Overlay is Active in Clone Mode
$CUI_Maintain_Aspect	1 bit		; Display "Maintain Aspect Ratio" via CUI
$Preserve_Aspect_Ratio	1 bit		; Preserve Aspect Ratio
$SDVO_Device_Power_Down	1 bit		; SDVO device Power down
$Hot_Plug_CRT		1 bit		; CRT hot plug
$LVDS_Config		2 bits		; LVDS configuration
$Hot_Plug_TV		1 bit		; Hot plug TV enable/disable
$INT_HDMI_Config	2 bits		; Integrated HDMI Configuration
ALIGN

			; bmp_Driver_Flags_1

$CUIHotK_Static_Display	1 bit
$Embedded_Platform	1 bit
$Disable_DisplayEnum	1 bit
SKIP		   	5 bits

$Legacy_Monitor_Max_X	2 bytes
$Legacy_Monitor_Max_Y	2 bytes
$Legacy_Monitor_Max_RR	1 bytes
ALIGN

			; bmp_Ext2_Driver_Bits

$Enable_Int_Src_Term	1 bit		; Enable Internal Source Termination for HDMI
SKIP		   	7 bits
ALIGN

$VBT_Customization_Version 1 byte	; Customization VBT version number

			; bmp_Driver_Feature_Flags

$PM_RMPM_Enable		1 bit		; Intel® Rapid Memory Power Management (RMPM) Enable/Disable Flag.
$PM_S2DDT_Enable 	1 bit	; Intel® Smart 2D Display Technology (S2DDT) Enable/Disable Flag.	

$PM_DPST_Enable		1 bit		; Intel® Display Power Saving Technology (DPST) Enable/Disable Flag.

$PM_BLC_Enable		1 bit		; Backlight Control (BLC) Enable/Disable Flag.

$PM_ADB_Enable		1 bit		; Intel® Automatic Display Brightness (ADB) Enable/Disable Flag.

$PM_DRRS_Enable		1 bit		; Intel® Display Refresh Rate Switching (DRRS) Enable/Disable Flag.
$PM_RS_Enable		1 bit		; Graphics Render Standby (RS) Enable/Disable Flag.
$PM_GPMT_Enable		1 bit		; Graphics Power Modulation Technology (GPMT) Enable/Disable Flag.
$PM_Turbo_Enable	1 bit		; Intel Turbo Boost Technology Enable/Disable Flag.
$Panel_Self_Refresh     1 bit           ; Panel Self refresh feature (PSR)
$Inter_Pixel_Storage	1 bit		; Intel Intermediate Pixel Storage Technology (IPS)
$Dynamic_FPS_Enable	1 bit		; Dynamic Frames per second(DFPS) feature Enable/Disable Flag.
$DMRRS				1 bit		; Dynamic media refresh rate enable/disable
$ADT					1 bit		; Assertive display technology enable/disable
SKIP		   			1 bit
$PC_Fields_Enable	1 bit		; PC Feature field's validity Flag.
ALIGN

  ;==============================================================================
  ; Block 13 - Driver Persistence Algorithm
  ;------------------------------------------------------------------------------

SKIP			  		3 bytes		; Skip block ID and size

  				; bmp_Persist_Algorithm

$Driver_Persist_Hotkey	  		1 bit
$Driver_Persist_Lid_Switch		1 bit
$Driver_Persist_PM	  		1 bit
$PersistHotkeyRestoreCloneMDS 		1 bit
$PersistHotkeyRestoreRefreshrate	1 bit
$PersistHotkeyRestorePipe		1 bit
$PersistHotkeyRestoreMode		1 bit
$PersistEDIDRestoreMode			1 bit
$PersistHotPlugRestoreMode		1 bit
$Driver_Persist_Docking			1 bit
SKIP		   			6 bits

ALIGN
$PersistMaxConfig			1 byte

;==============================================================================
; Block 14 - Pointer tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
SKIP			1 byte		; Number of tables

$Clock_Override_Table_Ptr	2 bytes
$Clock_Override_Table_Size	2 bytes
$Clock_Override_Table,		$Clock_Override_Table_Ptr, $Clock_Override_Table_Size, Offset 0 byte

$LVDS_Clock_Override_Tbl_Ptr	2 bytes
$LVDS_Clock_Override_Tbl_Size	2 bytes
$LVDS_Clock_Override_Tbl,	$LVDS_Clock_Override_Tbl_Ptr, $LVDS_Clock_Override_Tbl_Size, Offset 0 byte

;==============================================================================
; Block 15 - Dot Clock Override Table.
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
SKIP			2 bytes		; Table X and Y
SKIP			90 bytes	; Skip data
SKIP			47 bytes	; Skip LVDS data

  ;==============================================================================
  ; Block 16 - Obsolete (Was VBIOS/Driver Toggle list, capabilities tables)
  ;------------------------------------------------------------------------------

;==============================================================================
; Block 17 - Test Feature
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$SV_Dis_Arbiter		1 bit		; Disable VGA fast arbiter
$SV_Setmode_No_DVO	1 bit		; Do Setmode without reprogramming DVO
$SV_Special_GMBus	1 bit		; Special GMBus support
$SV_Wait_Timeout_Hang	1 bit
SKIP			4 bits
ALIGN
SKIP			7 bytes		; Skip reserved space

;==============================================================================
; Block 18 - Driver Rotation Configuration
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size
$Rot_Enable		1 bit		; Rotation Enable bit
SKIP			7 bits		
$Rot_Flags		1 byte		; obsoleted
SKIP			10 bytes	; Reserved

  ;==============================================================================
  ; Block 19 - Obsolete (Was removed Display Configurations)
  ;------------------------------------------------------------------------------

;==============================================================================
; Block 20 - OEM Customizable Modes
;------------------------------------------------------------------------------

SKIP			3  bytes		; Skip ID
SKIP			2  bytes		; Table Row/Size Data

$OEM_Mode_Flags1	1 byte
$OEM_Display_Flags1	1 byte
$OEM_Mode_X1		2 bytes
$OEM_Mode_Y1		2 bytes
$OEM_Mode_Color1	1 byte
$OEM_Mode_RRate1	1 byte
$OEM_Mode_DTD1		18 bytes

$OEM_Mode_Flags2	1 byte
$OEM_Display_Flags2	1 byte
$OEM_Mode_X2		2 bytes
$OEM_Mode_Y2		2 bytes
$OEM_Mode_Color2	1 byte
$OEM_Mode_RRate2	1 byte
$OEM_Mode_DTD2		18 bytes

$OEM_Mode_Flags3	1 byte
$OEM_Display_Flags3	1 byte
$OEM_Mode_X3		2 bytes
$OEM_Mode_Y3		2 bytes
$OEM_Mode_Color3	1 byte
$OEM_Mode_RRate3	1 byte
$OEM_Mode_DTD3		18 bytes

$OEM_Mode_Flags4	1 byte
$OEM_Display_Flags4	1 byte
$OEM_Mode_X4		2 bytes
$OEM_Mode_Y4		2 bytes
$OEM_Mode_Color4	1 byte
$OEM_Mode_RRate4	1 byte
$OEM_Mode_DTD4		18 bytes

$OEM_Mode_Flags5	1 byte
$OEM_Display_Flags5	1 byte
$OEM_Mode_X5		2 bytes
$OEM_Mode_Y5		2 bytes
$OEM_Mode_Color5	1 byte
$OEM_Mode_RRate5	1 byte
$OEM_Mode_DTD5		18 bytes

$OEM_Mode_Flags6	1 byte
$OEM_Display_Flags6	1 byte
$OEM_Mode_X6		2 bytes
$OEM_Mode_Y6		2 bytes
$OEM_Mode_Color6	1 byte
$OEM_Mode_RRate6	1 byte
$OEM_Mode_DTD6		18 bytes

;==============================================================================
; Block 22 - SDVO LVDS general parameters
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$LVDS_Init_Backlight 	1 byte
$LVDS_H40_Set_Panel_Type 1 byte
$LVDS_Panel_Type	1 byte
$LVDS_SSC_CLK_FREQ	1 byte
$LVDS_ALS_Low_Trip	2 bytes
$LVDS_ALS_High_Trip	2 bytes

SKIP			1 byte		; Skip Row Number
SKIP			1 byte		; Skip Row Size

$Scalar_Coef_0		1 byte
$Scalar_Coef_1		1 byte
$Scalar_Coef_2		1 byte
$Scalar_Coef_3		1 byte
$Scalar_Coef_4		1 byte
$Scalar_Coef_5		1 byte
$Scalar_Coef_6		1 byte
$Scalar_Coef_7		1 byte

		; LVDS_Misc_Bits_1.

$LVDS_Monitor_Hsync	1 bit
$LVDS_Monitor_Vsync	1 bit
$LVDS_Monitor_Pixel	1 bit
$LVDS_Panel_EDID	1 bit
$LVDS_Panel_Fitting	1 bit
$LVDS_Dither		1 bit
SKIP			2 bits

		; LVDS_Misc_Bits_2.

$LVDS_Panel_Color_Depth	2 bits
$LVDS_Panel_Connector	2 bits
$LVDS_Channel		2 bits
$LVDS_SSC_DualTwin_Disb	1 bit
$LVDS_SSC		1 bit

		; LVDS_Misc_Bits_3.

$LVDS_Panel_1_Channel_Type	1 bit
$LVDS_Panel_2_Channel_Type	1 bit
$LVDS_Panel_3_Channel_Type	1 bit
$LVDS_Panel_4_Channel_Type	1 bit
SKIP				4 bits

		; LVDS_Misc_Bits_4.

$LVDS_Panel_1_Color_Depth	2 bits
$LVDS_Panel_2_Color_Depth	2 bits
$LVDS_Panel_3_Color_Depth	2 bits
$LVDS_Panel_4_Color_Depth	2 bits
SKIP				1 byte

$SDVO_Panel_Name_01	13 bytes
$SDVO_Panel_Name_02	13 bytes
$SDVO_Panel_Name_03	13 bytes
$SDVO_Panel_Name_04	13 bytes

;==============================================================================
; Block 23 - SDVO Panel DTDs
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			18 bytes	; Panel#1 DTD
SKIP			18 bytes	; Panel#2 DTD
SKIP			18 bytes	; Panel#3 DTD
SKIP			18 bytes	; Panel#4 DTD

;==============================================================================
;  Block 24 - Tables of Panel PnP ID
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			10 bytes	; Panel#1 PnPID
SKIP			10 bytes	; Panel#2 PnPID
SKIP			10 bytes	; Panel#3 PnPID
SKIP			10 bytes	; Panel#4 PnPID

;==============================================================================
; Block 25 - SDVO LVDS Power Sequencing
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

SKIP			10 bytes	; Panel#1 Power Sequencing
SKIP			10 bytes	; Panel#2 Power Sequencing
SKIP			10 bytes	; Panel#3 Power Sequencing
SKIP			10 bytes	; Panel#4 Power Sequencing

;==============================================================================
; Block 26 - TV features
;------------------------------------------------------------------------------
SKIP			3  bytes	; Skip ID and size
$Under_Over_Scan_Via_YPrPb 2 bits	; Underscan/overscan for HDTV via YPrPb
SKIP			10 bits
$Under_Over_Scan_Via_DVI 2 bits		; Underscan/overscan for HDTV via DVI
$Add_Overscan_Mode 	1 bit		; Add modes to avoid overscan issue
$D_Connector		1 bit		; D-Connector Support
ALIGN

#IF	$eDP == 1	; $eDP == TRUE
  ;==============================================================================
  ; Block 27 - eDP Power Sequencing
  ;------------------------------------------------------------------------------
  SKIP			3 bytes		; Skip block ID and size

  
	; Panel#1 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_01				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_01		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_01	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_01		2 bytes
	$eDP_PowerCycle_Delay_01 				2 bytes

	; Panel#2 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_02				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_02		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_02	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_02		2 bytes
	$eDP_PowerCycle_Delay_02 				2 bytes

	; Panel#3 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_03				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_03		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_03	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_03		2 bytes
	$eDP_PowerCycle_Delay_03 				2 bytes

	; Panel#4 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_04				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_04		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_04	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_04		2 bytes
	$eDP_PowerCycle_Delay_04 				2 bytes

	; Panel#5 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_05				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_05		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_05	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_05		2 bytes
	$eDP_PowerCycle_Delay_05 				2 bytes

	; Panel#6 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_06				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_06		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_06	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_06		2 bytes
	$eDP_PowerCycle_Delay_06 				2 bytes

	; Panel#7 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_07				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_07		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_07	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_07		2 bytes
	$eDP_PowerCycle_Delay_07 				2 bytes

	; Panel#8 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_08				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_08		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_08	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_08		2 bytes
	$eDP_PowerCycle_Delay_08 				2 bytes

	; Panel#9 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_09				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_09		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_09	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_09		2 bytes
	$eDP_PowerCycle_Delay_09				2 bytes

	; Panel#10 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_10				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_10		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_10	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_10		2 bytes	
	$eDP_PowerCycle_Delay_10 				2 bytes

	; Panel#11 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_11				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_11		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_11	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_11		2 bytes
	$eDP_PowerCycle_Delay_11 				2 bytes

	; Panel#12 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_12				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_12		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_12	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_12		2 bytes
	$eDP_PowerCycle_Delay_12 				2 bytes

	; Panel#13 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_13				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_13		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_13	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_13		2 bytes
	$eDP_PowerCycle_Delay_13 				2 bytes

	; Panel#14 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_14				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_14		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_14	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_14		2 bytes
	$eDP_PowerCycle_Delay_14 				2 bytes

	; Panel#15 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_15				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_15		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_15	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_15		2 bytes
	$eDP_PowerCycle_Delay_15 				2 bytes

	; Panel#16 Power Sequencing
	$eDP_Vcc_To_Hpd_Delay_16				2 bytes        
	$eDP_DataOn_To_BkltEnable_Delay_16		2 bytes
	$eDP_BkltDisable_To_DataOff_Delay_16	2 bytes
	$eDP_DataOff_To_PowerOff_Delay_16		2 bytes
	$eDP_PowerCycle_Delay_16 				2 bytes

  $eDP_Panel_Color_Depth_01	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_02	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_03	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_04	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_05	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_06	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_07	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_08	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_09	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_10	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_11	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_12	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_13	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_14	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_15	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp
  $eDP_Panel_Color_Depth_16	2 bits	; 00 = 18bpp, 01 = 24bpp, 10 = 30bpp

  $eDP_Link_DataRate_01		4 bits	; Panel #1 Link Data Rate
  $eDP_Link_LaneCount_01	4 bits	; Panel #1 Link Lane Count
  $eDP_Link_PreEmp_01		4 bits	; Panel #1 Link Pre-Emphasis 
  $eDP_Link_VSwing_01		4 bits	; Panel #1 Link Voltage Swing

  $eDP_Link_DataRate_02		4 bits	; Panel #2 Link Data Rate
  $eDP_Link_LaneCount_02	4 bits	; Panel #2 Link Lane Count
  $eDP_Link_PreEmp_02		4 bits	; Panel #2 Link Pre-Emphasis 
  $eDP_Link_VSwing_02		4 bits	; Panel #2 Link Voltage Swing

  $eDP_Link_DataRate_03		4 bits	; Panel #3 Link Data Rate
  $eDP_Link_LaneCount_03	4 bits	; Panel #3 Link Lane Count
  $eDP_Link_PreEmp_03		4 bits	; Panel #3 Link Pre-Emphasis 
  $eDP_Link_VSwing_03		4 bits	; Panel #3 Link Voltage Swing

  $eDP_Link_DataRate_04		4 bits	; Panel #4 Link Data Rate	
  $eDP_Link_LaneCount_04	4 bits 	; Panel #4 Link Lane Count	
  $eDP_Link_PreEmp_04		4 bits	; Panel #4 Link Pre-Emphasis 
  $eDP_Link_VSwing_04		4 bits	; Panel #4 Link Voltage Swing

  $eDP_Link_DataRate_05		4 bits	; Panel #5 Link Data Rate
  $eDP_Link_LaneCount_05	4 bits	; Panel #5 Link Lane Count
  $eDP_Link_PreEmp_05		4 bits	; Panel #5 Link Pre-Emphasis 
  $eDP_Link_VSwing_05		4 bits	; Panel #5 Link Voltage Swing

  $eDP_Link_DataRate_06		4 bits	; Panel #6 Link Data Rate
  $eDP_Link_LaneCount_06	4 bits	; Panel #6 Link Lane Count
  $eDP_Link_PreEmp_06		4 bits	; Panel #6 Link Pre-Emphasis 
  $eDP_Link_VSwing_06		4 bits	; Panel #6 Link Voltage Swing

  $eDP_Link_DataRate_07		4 bits	; Panel #7 Link Data Rate
  $eDP_Link_LaneCount_07	4 bits	; Panel #7 Link Lane Count
  $eDP_Link_PreEmp_07		4 bits	; Panel #7 Link Pre-Emphasis 
  $eDP_Link_VSwing_07		4 bits	; Panel #7 Link Voltage Swing

  $eDP_Link_DataRate_08		4 bits	; Panel #8 Link Data Rate
  $eDP_Link_LaneCount_08	4 bits	; Panel #8 Link Lane Count
  $eDP_Link_PreEmp_08		4 bits	; Panel #8 Link Pre-Emphasis 
  $eDP_Link_VSwing_08		4 bits	; Panel #8 Link Voltage Swing

  $eDP_Link_DataRate_09		4 bits	; Panel #9 Link Data Rate
  $eDP_Link_LaneCount_09	4 bits	; Panel #9 Link Lane Count
  $eDP_Link_PreEmp_09		4 bits	; Panel #9 Link Pre-Emphasis 
  $eDP_Link_VSwing_09		4 bits	; Panel #9 Link Voltage Swing

  $eDP_Link_DataRate_10		4 bits	; Panel #10 Link Data Rate
  $eDP_Link_LaneCount_10	4 bits	; Panel #10 Link Lane Count
  $eDP_Link_PreEmp_10		4 bits	; Panel #10 Link Pre-Emphasis 
  $eDP_Link_VSwing_10		4 bits	; Panel #10 Link Voltage Swing

  $eDP_Link_DataRate_11		4 bits	; Panel #11 Link Data Rate
  $eDP_Link_LaneCount_11	4 bits	; Panel #11 Link Lane Count
  $eDP_Link_PreEmp_11		4 bits	; Panel #11 Link Pre-Emphasis 
  $eDP_Link_VSwing_11		4 bits	; Panel #11 Link Voltage Swing

  $eDP_Link_DataRate_12		4 bits	; Panel #12 Link Data Rate
  $eDP_Link_LaneCount_12	4 bits	; Panel #12 Link Lane Count
  $eDP_Link_PreEmp_12		4 bits	; Panel #12 Link Pre-Emphasis 
  $eDP_Link_VSwing_12		4 bits	; Panel #12 Link Voltage Swing

  $eDP_Link_DataRate_13		4 bits	; Panel #13 Link Data Rate
  $eDP_Link_LaneCount_13	4 bits	; Panel #13 Link Lane Count
  $eDP_Link_PreEmp_13		4 bits	; Panel #13 Link Pre-Emphasis 
  $eDP_Link_VSwing_13		4 bits	; Panel #13 Link Voltage Swing

  $eDP_Link_DataRate_14		4 bits	; Panel #14 Link Data Rate
  $eDP_Link_LaneCount_14	4 bits	; Panel #14 Link Lane Count
  $eDP_Link_PreEmp_14		4 bits	; Panel #14 Link Pre-Emphasis 
  $eDP_Link_VSwing_14		4 bits	; Panel #14 Link Voltage Swing

  $eDP_Link_DataRate_15		4 bits	; Panel #15 Link Data Rate
  $eDP_Link_LaneCount_15	4 bits	; Panel #15 Link Lane Count
  $eDP_Link_PreEmp_15		4 bits	; Panel #15 Link Pre-Emphasis 
  $eDP_Link_VSwing_15		4 bits	; Panel #15 Link Voltage Swing

  $eDP_Link_DataRate_16		4 bits	; Panel #16 Link Data Rate
  $eDP_Link_LaneCount_16	4 bits	; Panel #16 Link Lane Count
  $eDP_Link_PreEmp_16		4 bits	; Panel #16 Link Pre-Emphasis 
  $eDP_Link_VSwing_16		4 bits	; Panel #16 Link Voltage Swing

  $eDP_sDRRS_MSA_Delay_01		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_02		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_03		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_04		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_05		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_06		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_07		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_08		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_09		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_10		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_11		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_12		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_13		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_14		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_15		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4
  $eDP_sDRRS_MSA_Delay_16		2 bits	; 00 = Line 1, 01 = Line 2, 10 = Line 3, 11 = Line 4

  $edp_S3D_Feature_01	1 bit		; S3D enable disable VBT bit panel #01
  $edp_S3D_Feature_02	1 bit		; S3D enable disable VBT bit panel #02
  $edp_S3D_Feature_03	1 bit		; S3D enable disable VBT bit panel #03
  $edp_S3D_Feature_04	1 bit		; S3D enable disable VBT bit panel #04
  $edp_S3D_Feature_05	1 bit		; S3D enable disable VBT bit panel #05
  $edp_S3D_Feature_06	1 bit		; S3D enable disable VBT bit panel #06
  $edp_S3D_Feature_07	1 bit		; S3D enable disable VBT bit panel #07
  $edp_S3D_Feature_08	1 bit		; S3D enable disable VBT bit panel #08
  $edp_S3D_Feature_09	1 bit		; S3D enable disable VBT bit panel #09
  $edp_S3D_Feature_10	1 bit		; S3D enable disable VBT bit panel #10
  $edp_S3D_Feature_11	1 bit		; S3D enable disable VBT bit panel #11
  $edp_S3D_Feature_12	1 bit		; S3D enable disable VBT bit panel #12
  $edp_S3D_Feature_13	1 bit		; S3D enable disable VBT bit panel #13
  $edp_S3D_Feature_14	1 bit		; S3D enable disable VBT bit panel #14
  $edp_S3D_Feature_15	1 bit		; S3D enable disable VBT bit panel #15
  $edp_S3D_Feature_16	1 bit		; S3D enable disable VBT bit panel #16

  $eDP_T3_Optimization_01	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #01
  $eDP_T3_Optimization_02	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #02
  $eDP_T3_Optimization_03	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #03
  $eDP_T3_Optimization_04	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #04
  $eDP_T3_Optimization_05	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #05
  $eDP_T3_Optimization_06	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #06
  $eDP_T3_Optimization_07	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #07
  $eDP_T3_Optimization_08	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #08
  $eDP_T3_Optimization_09	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #09
  $eDP_T3_Optimization_10	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #10
  $eDP_T3_Optimization_11	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #11
  $eDP_T3_Optimization_12	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #12
  $eDP_T3_Optimization_13	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #13
  $eDP_T3_Optimization_14	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #14
  $eDP_T3_Optimization_15	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #15
  $eDP_T3_Optimization_16	1 bit	; eDP T3 Optimization enable disabled VBT bit panel #16
  
  $eDP_VSwingPreEmph_1       4 bits; eDp selects VSwing Preemph table for panel #1
  $eDP_VSwingPreEmph_2       4 bits; eDp selects VSwing Preemph table for panel #2
  $eDP_VSwingPreEmph_3       4 bits; eDp selects VSwing Preemph table for panel #3
  $eDP_VSwingPreEmph_4       4 bits; eDp selects VSwing Preemph table for panel #4
  $eDP_VSwingPreEmph_5       4 bits; eDp selects VSwing Preemph table for panel #5
  $eDP_VSwingPreEmph_6       4 bits; eDp selects VSwing Preemph table for panel #6
  $eDP_VSwingPreEmph_7       4 bits; eDp selects VSwing Preemph table for panel #7
  $eDP_VSwingPreEmph_8       4 bits; eDp selects VSwing Preemph table for panel #8
  $eDP_VSwingPreEmph_9       4 bits; eDp selects VSwing Preemph table for panel #9
  $eDP_VSwingPreEmph_10       4 bits; eDp selects VSwing Preemph table for panel #10
  $eDP_VSwingPreEmph_11       4 bits; eDp selects VSwing Preemph table for panel #11
  $eDP_VSwingPreEmph_12       4 bits; eDp selects VSwing Preemph table for panel #12
  $eDP_VSwingPreEmph_13       4 bits; eDp selects VSwing Preemph table for panel #13
  $eDP_VSwingPreEmph_14       4 bits; eDp selects VSwing Preemph table for panel #14
  $eDP_VSwingPreEmph_15       4 bits; eDp selects VSwing Preemph table for panel #15
  $eDP_VSwingPreEmph_16       4 bits; eDp selects VSwing Preemph table for panel #16
  
  $Fast_Link_Training_Supported_01 1 bit
  $Fast_Link_Training_Supported_02 1 bit
  $Fast_Link_Training_Supported_03 1 bit
  $Fast_Link_Training_Supported_04 1 bit
  $Fast_Link_Training_Supported_05 1 bit
  $Fast_Link_Training_Supported_06 1 bit
  $Fast_Link_Training_Supported_07 1 bit
  $Fast_Link_Training_Supported_08 1 bit
  $Fast_Link_Training_Supported_09 1 bit
  $Fast_Link_Training_Supported_10 1 bit
  $Fast_Link_Training_Supported_11 1 bit
  $Fast_Link_Training_Supported_12 1 bit
  $Fast_Link_Training_Supported_13 1 bit
  $Fast_Link_Training_Supported_14 1 bit
  $Fast_Link_Training_Supported_15 1 bit
  $Fast_Link_Training_Supported_16 1 bit
  
  SKIP 	                                  2 bytes ;Skip Enable Power State at DPCD 600h

  $eDP_PwmOn_To_Bklt_Enable_Delay_01 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#1
  $eDP_Bklt_Disable_To_PwmOff_Delay_01	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#1

  $eDP_PwmOn_To_Bklt_Enable_Delay_02 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#2
  $eDP_Bklt_Disable_To_PwmOff_Delay_02	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#2

  $eDP_PwmOn_To_Bklt_Enable_Delay_03 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#3
  $eDP_Bklt_Disable_To_PwmOff_Delay_03	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#3
 
  $eDP_PwmOn_To_Bklt_Enable_Delay_04 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#4
  $eDP_Bklt_Disable_To_PwmOff_Delay_04	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#4

  $eDP_PwmOn_To_Bklt_Enable_Delay_05 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#5
  $eDP_Bklt_Disable_To_PwmOff_Delay_05	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#5

  $eDP_PwmOn_To_Bklt_Enable_Delay_06 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#6
  $eDP_Bklt_Disable_To_PwmOff_Delay_06	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#6

  $eDP_PwmOn_To_Bklt_Enable_Delay_07 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#7
  $eDP_Bklt_Disable_To_PwmOff_Delay_07	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#7

  $eDP_PwmOn_To_Bklt_Enable_Delay_08 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#8
  $eDP_Bklt_Disable_To_PwmOff_Delay_08	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#8

  $eDP_PwmOn_To_Bklt_Enable_Delay_09 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#9
  $eDP_Bklt_Disable_To_PwmOff_Delay_09	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#9

  $eDP_PwmOn_To_Bklt_Enable_Delay_10 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#10
  $eDP_Bklt_Disable_To_PwmOff_Delay_10	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#10

  $eDP_PwmOn_To_Bklt_Enable_Delay_11 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#11
  $eDP_Bklt_Disable_To_PwmOff_Delay_11	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#11

  $eDP_PwmOn_To_Bklt_Enable_Delay_12 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#12
  $eDP_Bklt_Disable_To_PwmOff_Delay_12	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#12

  $eDP_PwmOn_To_Bklt_Enable_Delay_13 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#13
  $eDP_Bklt_Disable_To_PwmOff_Delay_13	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#13

  $eDP_PwmOn_To_Bklt_Enable_Delay_14 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#14
  $eDP_Bklt_Disable_To_PwmOff_Delay_14	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#14

  $eDP_PwmOn_To_Bklt_Enable_Delay_15 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#15
  $eDP_Bklt_Disable_To_PwmOff_Delay_15	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#15

  $eDP_PwmOn_To_Bklt_Enable_Delay_16 	  2 bytes ; Delay from Pwm On to Backlight Enable for Panel#16
  $eDP_Bklt_Disable_To_PwmOff_Delay_16	  2 bytes ; Delay from Backlight Disable to Pwm Off for Panle#16
#ENDIF	; $eDP == 1	; $eDP == TRUE

;==============================================================================
; Block 28 - EDID-less EFP support - Panel data
;------------------------------------------------------------------------------
SKIP			3 bytes		; Skip block ID and size

				; Panel for Device 1
$EFP1_DTD		18 bytes	; DTD for Device 1 DP/DVI panel
				; Panel for Device 2
$EFP2_DTD		18 bytes	; DTD for Device 2 DP/DVI panel
				; Panel for Device 3
$EFP3_DTD		18 bytes	; DTD for Device 3 DP/DVI panel

  ;==============================================================================
  ; Block 29 - VBIOS/Driver Toggle list for IVM and above, capabilities tables
  ;------------------------------------------------------------------------------

SKIP			3  bytes		; Skip block ID and size
SKIP			52 bytes		; Skip Toggle lists
ALIGN

  ;==============================================================================
  ; Block 30 - Removed Display Configurations for IVM and above
  ;------------------------------------------------------------------------------

SKIP			3  bytes		; Skip block ID and size
SKIP			2  bytes		; Table Row/Size Data
SKIP			15  bytes		; Skip Removed displays table

;==============================================================================
; Block 31 - VBIOS/Driver Toggle list for HSW/BDW
;------------------------------------------------------------------------------

  SKIP			3  bytes		; Skip block ID and size
  SKIP			92 bytes		; Skip Toggle lists
  ALIGN

;==============================================================================
; Block 32 - Was Display Configurations for HSW/BDW
;------------------------------------------------------------------------------
  SKIP			3  bytes		; Skip block ID and size
  SKIP			2  bytes		; Table Row/Size Data
  SKIP			30  bytes		; Skip Removed displays table

;==============================================================================
; Block 40 - Start of LVDS BMP Structure Definition
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

$bmp_Panel_type		1 byte		; Flat panel type
SKIP			1 byte		; Obsoleted
SKIP			6 bits
$bmp_Panel_EDID		1 bit		; LVDS panel EDID enable/disable bit

SKIP			1 bit
SKIP			1 byte

		; INT_LVDS_Panel_Channel_Bits

$Int_LVDS_Panel_1_Channel_Type	2 bits	; Bits [2:3] = Panel #1
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_2_Channel_Type	2 bits	; Bits [2:3] = Panel #2
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_3_Channel_Type	2 bits	; Bits [2:3] = Panel #3
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_4_Channel_Type	2 bits	; Bits [2:3] = Panel #4
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_5_Channel_Type	2 bits	; Bits [2:3] = Panel #5
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_6_Channel_Type	2 bits	; Bits [2:3] = Panel #6
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_7_Channel_Type	2 bits	; Bits [2:3] = Panel #7
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_8_Channel_Type	2 bits	; Bits [2:3] = Panel #8
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_9_Channel_Type	2 bits	; Bits [2:3] = Panel #9
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_10_Channel_Type	2 bits	; Bits [2:3] = Panel #10
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_11_Channel_Type	2 bits	; Bits [2:3] = Panel #11
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_12_Channel_Type	2 bits	; Bits [2:3] = Panel #12
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_13_Channel_Type	2 bits	; Bits [2:3] = Panel #13
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_14_Channel_Type	2 bits	; Bits [2:3] = Panel #14
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_15_Channel_Type	2 bits	; Bits [2:3] = Panel #15
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved
$Int_LVDS_Panel_16_Channel_Type	2 bits	; Bits [2:3] = Panel #16
					;	= 00, Automatic (algorithm)
					;	= 01, Single Channel
					;	= 10, Dual Channel
					;	= 11, Reserved

					; LVDS Spread Spectrum Clock
					; Enabel/Disable SSC
$Enable_SSC01		1 bit		; Panel #01, 0=No, 1=Yes
$Enable_SSC02		1 bit		; Panel #02, 0=No, 1=Yes
$Enable_SSC03		1 bit		; Panel #03, 0=No, 1=Yes
$Enable_SSC04		1 bit		; Panel #04, 0=No, 1=Yes
$Enable_SSC05		1 bit		; Panel #05, 0=No, 1=Yes
$Enable_SSC06		1 bit		; Panel #06, 0=No, 1=Yes
$Enable_SSC07		1 bit		; Panel #07, 0=No, 1=Yes
$Enable_SSC08		1 bit		; Panel #08, 0=No, 1=Yes
$Enable_SSC09		1 bit		; Panel #09, 0=No, 1=Yes
$Enable_SSC10		1 bit		; Panel #10, 0=No 1=Yes
$Enable_SSC11		1 bit		; Panel #11, 0=No, 1=Yes
$Enable_SSC12		1 bit		; Panel #12, 0=No, 1=Yes
$Enable_SSC13		1 bit		; Panel #13, 0=No, 1=Yes
$Enable_SSC14		1 bit		; Panel #14, 0=No, 1=Yes
$Enable_SSC15		1 bit		; Panel #15, 0=No, 1=Yes
$Enable_SSC16		1 bit		; Panel #16, 0=No, 1=Yes

					; LVDS Spread Spectrum Clock Frequency
					; SSC Frequency
$SSC_Freq01		1 bit		; Panel #01, 0=48MHz, 1=66MHz
$SSC_Freq02		1 bit		; Panel #02, 0=48MHz, 1=66MHz
$SSC_Freq03		1 bit		; Panel #03, 0=48MHz, 1=66MHz
$SSC_Freq04		1 bit		; Panel #04, 0=48MHz, 1=66MHz
$SSC_Freq05		1 bit		; Panel #05, 0=48MHz, 1=66MHz
$SSC_Freq06		1 bit		; Panel #06, 0=48MHz, 1=66MHz
$SSC_Freq07		1 bit		; Panel #07, 0=48MHz, 1=66MHz
$SSC_Freq08		1 bit		; Panel #08, 0=48MHz, 1=66MHz
$SSC_Freq09		1 bit		; Panel #09, 0=48MHz, 1=66MHz
$SSC_Freq10		1 bit		; Panel #10, 0=48MHz, 1=66MHz
$SSC_Freq11		1 bit		; Panel #11, 0=48MHz, 1=66MHz
$SSC_Freq12		1 bit		; Panel #12, 0=48MHz, 1=66MHz
$SSC_Freq13		1 bit		; Panel #13, 0=48MHz, 1=66MHz
$SSC_Freq14		1 bit		; Panel #14, 0=48MHz, 1=66MHz
$SSC_Freq15		1 bit		; Panel #15, 0=48MHz, 1=66MHz
$SSC_Freq16		1 bit		; Panel #16, 0=48MHz, 1=66MHz

					; Disable SSC in Dual Display Twin
$Disable_SSC_DDT01	1 bit		; panel #01, 0=Disable, 1=Enable
$Disable_SSC_DDT02	1 bit		; panel #02, 0=Disable, 1=Enable
$Disable_SSC_DDT03	1 bit		; panel #03, 0=Disable, 1=Enable
$Disable_SSC_DDT04	1 bit		; panel #04, 0=Disable, 1=Enable
$Disable_SSC_DDT05	1 bit		; panel #05, 0=Disable, 1=Enable
$Disable_SSC_DDT06	1 bit		; panel #06, 0=Disable, 1=Enable
$Disable_SSC_DDT07	1 bit		; panel #07, 0=Disable, 1=Enable
$Disable_SSC_DDT08	1 bit		; panel #08, 0=Disable, 1=Enable
$Disable_SSC_DDT09	1 bit		; panel #09, 0=Disable, 1=Enable
$Disable_SSC_DDT10	1 bit		; panel #10, 0=Disable, 1=Enable
$Disable_SSC_DDT11	1 bit		; panel #11, 0=Disable, 1=Enable
$Disable_SSC_DDT12	1 bit		; panel #12, 0=Disable, 1=Enable
$Disable_SSC_DDT13	1 bit		; panel #13, 0=Disable, 1=Enable
$Disable_SSC_DDT14	1 bit		; panel #14, 0=Disable, 1=Enable
$Disable_SSC_DDT15	1 bit		; panel #15, 0=Disable, 1=Enable
$Disable_SSC_DDT16	1 bit		; panel #16, 0=Disable, 1=Enable

$INT_Panel_Color_Depth01	1 bit		; Panel #01, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth02	1 bit		; Panel #02, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth03	1 bit		; Panel #03, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth04	1 bit		; Panel #04, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth05	1 bit		; Panel #05, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth06	1 bit		; Panel #06, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth07	1 bit		; Panel #07, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth08	1 bit		; Panel #08, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth09	1 bit		; Panel #09, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth10	1 bit		; Panel #10, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth11	1 bit		; Panel #11, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth12	1 bit		; Panel #12, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth13	1 bit		; Panel #13, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth14	1 bit		; Panel #14, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth15	1 bit		; Panel #15, 0 = 18bpps, 1 = 24bpps
$INT_Panel_Color_Depth16	1 bit		; Panel #16, 0 = 18bpps, 1 = 24bpps

$DPS_Panel_Type_01		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_02		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_03		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_04		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_05		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_06		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_07		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_08		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_09		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_10		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_11		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_12		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_13		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_14		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_15		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless
$DPS_Panel_Type_16		2 bits		; 00 = Static DRRS, 01 = Redundant, 10 = Seamless

$Blt_Control_01		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_02		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_03		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_04		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_05		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_06		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_07		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_08		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_09		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_10		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_11		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_12		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_13		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_14		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_15		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight
$Blt_Control_16		2 bits		; 00 = Default, 01 = CCFL backlight, 10 = LED backlight

;==============================================================================
; Block 41 - Flat Panel Data Tables Pointers
;------------------------------------------------------------------------------

SKIP			3 bytes		; SKIP block ID and size
SKIP			1 byte		; Skip entries number byte

$LVDS_Tbl_Ptr_01	2 bytes
$LVDS_Tbl_Size_01	1 byte
$LVDS_Tbl_01,		$LVDS_Tbl_Ptr_01, $LVDS_Tbl_Size_01, Offset 4 bytes
$DVO_Tbl_Ptr_01		2 bytes
$DVO_Tbl_Size_01	1 byte
$DVO_Tbl_01,		$DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte
$LVDS_PnP_ID_Ptr_01	2 bytes
$LVDS_PnP_ID_Size_01	1 byte
$LVDS_PnP_ID_01,	$LVDS_PnP_ID_Ptr_01, $LVDS_PnP_ID_Size_01, Offset 0 byte

$LVDS_Tbl_Ptr_02	2 bytes
$LVDS_Tbl_Size_02	1 byte
$LVDS_Tbl_02,		$LVDS_Tbl_Ptr_02, $LVDS_Tbl_Size_02, Offset 4 bytes
$DVO_Tbl_Ptr_02		2 bytes
$DVO_Tbl_Size_02	1 byte
$DVO_Tbl_02,		$DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte
$LVDS_PnP_ID_Ptr_02	2 bytes
$LVDS_PnP_ID_Size_02	1 byte
$LVDS_PnP_ID_02,	$LVDS_PnP_ID_Ptr_02, $LVDS_PnP_ID_Size_02, Offset 0 byte

$LVDS_Tbl_Ptr_03	2 bytes
$LVDS_Tbl_Size_03	1 byte
$LVDS_Tbl_03,		$LVDS_Tbl_Ptr_03, $LVDS_Tbl_Size_03, Offset 4 bytes
$DVO_Tbl_Ptr_03		2 bytes
$DVO_Tbl_Size_03	1 byte
$DVO_Tbl_03,		$DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte
$LVDS_PnP_ID_Ptr_03	2 bytes
$LVDS_PnP_ID_Size_03	1 byte
$LVDS_PnP_ID_03,	$LVDS_PnP_ID_Ptr_03, $LVDS_PnP_ID_Size_03, Offset 0 byte

$LVDS_Tbl_Ptr_04	2 bytes
$LVDS_Tbl_Size_04	1 byte
$LVDS_Tbl_04,		$LVDS_Tbl_Ptr_04, $LVDS_Tbl_Size_04, Offset 4 bytes
$DVO_Tbl_Ptr_04		2 bytes
$DVO_Tbl_Size_04	1 byte
$DVO_Tbl_04,		$DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte
$LVDS_PnP_ID_Ptr_04	2 bytes
$LVDS_PnP_ID_Size_04	1 byte
$LVDS_PnP_ID_04,	$LVDS_PnP_ID_Ptr_04, $LVDS_PnP_ID_Size_04, Offset 0 byte

$LVDS_Tbl_Ptr_05	2 bytes
$LVDS_Tbl_Size_05	1 byte
$LVDS_Tbl_05,		$LVDS_Tbl_Ptr_05, $LVDS_Tbl_Size_05, Offset 4 bytes
$DVO_Tbl_Ptr_05		2 bytes
$DVO_Tbl_Size_05	1 byte
$DVO_Tbl_05,		$DVO_Tbl_Ptr_05, $DVO_Tbl_Size_05, Offset 0 byte
$LVDS_PnP_ID_Ptr_05	2 bytes
$LVDS_PnP_ID_Size_05	1 byte
$LVDS_PnP_ID_05,	$LVDS_PnP_ID_Ptr_05, $LVDS_PnP_ID_Size_05, Offset 0 byte

$LVDS_Tbl_Ptr_06	2 bytes
$LVDS_Tbl_Size_06	1 byte
$LVDS_Tbl_06,		$LVDS_Tbl_Ptr_06, $LVDS_Tbl_Size_06, Offset 4 bytes
$DVO_Tbl_Ptr_06		2 bytes
$DVO_Tbl_Size_06	1 byte
$DVO_Tbl_06,		$DVO_Tbl_Ptr_06, $DVO_Tbl_Size_06, Offset 0 byte
$LVDS_PnP_ID_Ptr_06	2 bytes
$LVDS_PnP_ID_Size_06	1 byte
$LVDS_PnP_ID_06,	$LVDS_PnP_ID_Ptr_06, $LVDS_PnP_ID_Size_06, Offset 0 byte

$LVDS_Tbl_Ptr_07	2 bytes
$LVDS_Tbl_Size_07	1 byte
$LVDS_Tbl_07,		$LVDS_Tbl_Ptr_07, $LVDS_Tbl_Size_07, Offset 4 bytes
$DVO_Tbl_Ptr_07		2 bytes
$DVO_Tbl_Size_07	1 byte
$DVO_Tbl_07,		$DVO_Tbl_Ptr_07, $DVO_Tbl_Size_07, Offset 0 byte
$LVDS_PnP_ID_Ptr_07	2 bytes
$LVDS_PnP_ID_Size_07	1 byte
$LVDS_PnP_ID_07,	$LVDS_PnP_ID_Ptr_07, $LVDS_PnP_ID_Size_07, Offset 0 byte

$LVDS_Tbl_Ptr_08	2 bytes
$LVDS_Tbl_Size_08	1 byte
$LVDS_Tbl_08,		$LVDS_Tbl_Ptr_08, $LVDS_Tbl_Size_08, Offset 4 bytes
$DVO_Tbl_Ptr_08		2 bytes
$DVO_Tbl_Size_08	1 byte
$DVO_Tbl_08,		$DVO_Tbl_Ptr_08, $DVO_Tbl_Size_08, Offset 0 byte
$LVDS_PnP_ID_Ptr_08	2 bytes
$LVDS_PnP_ID_Size_08	1 byte
$LVDS_PnP_ID_08,	$LVDS_PnP_ID_Ptr_08, $LVDS_PnP_ID_Size_08, Offset 0 byte

$LVDS_Tbl_Ptr_09	2 bytes
$LVDS_Tbl_Size_09	1 byte
$LVDS_Tbl_09,		$LVDS_Tbl_Ptr_09, $LVDS_Tbl_Size_09, Offset 4 bytes
$DVO_Tbl_Ptr_09		2 bytes
$DVO_Tbl_Size_09	1 byte
$DVO_Tbl_09,		$DVO_Tbl_Ptr_09, $DVO_Tbl_Size_09, Offset 0 byte
$LVDS_PnP_ID_Ptr_09	2 bytes
$LVDS_PnP_ID_Size_09	1 byte
$LVDS_PnP_ID_09,	$LVDS_PnP_ID_Ptr_09, $LVDS_PnP_ID_Size_09, Offset 0 byte

$LVDS_Tbl_Ptr_10	2 bytes
$LVDS_Tbl_Size_10	1 byte
$LVDS_Tbl_10,		$LVDS_Tbl_Ptr_10, $LVDS_Tbl_Size_10, Offset 4 bytes
$DVO_Tbl_Ptr_10		2 bytes
$DVO_Tbl_Size_10	1 byte
$DVO_Tbl_10,		$DVO_Tbl_Ptr_10, $DVO_Tbl_Size_10, Offset 0 byte
$LVDS_PnP_ID_Ptr_10	2 bytes
$LVDS_PnP_ID_Size_10	1 byte
$LVDS_PnP_ID_10,	$LVDS_PnP_ID_Ptr_10, $LVDS_PnP_ID_Size_10, Offset 0 byte

$LVDS_Tbl_Ptr_11	2 bytes
$LVDS_Tbl_Size_11	1 byte
$LVDS_Tbl_11,		$LVDS_Tbl_Ptr_11, $LVDS_Tbl_Size_11, Offset 4 bytes
$DVO_Tbl_Ptr_11		2 bytes
$DVO_Tbl_Size_11	1 byte
$DVO_Tbl_11,		$DVO_Tbl_Ptr_11, $DVO_Tbl_Size_11, Offset 0 byte
$LVDS_PnP_ID_Ptr_11	2 bytes
$LVDS_PnP_ID_Size_11	1 byte
$LVDS_PnP_ID_11,	$LVDS_PnP_ID_Ptr_11, $LVDS_PnP_ID_Size_11, Offset 0 byte

$LVDS_Tbl_Ptr_12	2 bytes
$LVDS_Tbl_Size_12	1 byte
$LVDS_Tbl_12,		$LVDS_Tbl_Ptr_12, $LVDS_Tbl_Size_12, Offset 4 bytes
$DVO_Tbl_Ptr_12		2 bytes
$DVO_Tbl_Size_12	1 byte
$DVO_Tbl_12,		$DVO_Tbl_Ptr_12, $DVO_Tbl_Size_12, Offset 0 byte
$LVDS_PnP_ID_Ptr_12	2 bytes
$LVDS_PnP_ID_Size_12	1 byte
$LVDS_PnP_ID_12,	$LVDS_PnP_ID_Ptr_12, $LVDS_PnP_ID_Size_12, Offset 0 byte

$LVDS_Tbl_Ptr_13	2 bytes
$LVDS_Tbl_Size_13	1 byte
$LVDS_Tbl_13,		$LVDS_Tbl_Ptr_13, $LVDS_Tbl_Size_13, Offset 4 bytes
$DVO_Tbl_Ptr_13		2 bytes
$DVO_Tbl_Size_13	1 byte
$DVO_Tbl_13,		$DVO_Tbl_Ptr_13, $DVO_Tbl_Size_13, Offset 0 byte
$LVDS_PnP_ID_Ptr_13	2 bytes
$LVDS_PnP_ID_Size_13	1 byte
$LVDS_PnP_ID_13,	$LVDS_PnP_ID_Ptr_13, $LVDS_PnP_ID_Size_13, Offset 0 byte

$LVDS_Tbl_Ptr_14	2 bytes
$LVDS_Tbl_Size_14	1 byte
$LVDS_Tbl_14,		$LVDS_Tbl_Ptr_14, $LVDS_Tbl_Size_14, Offset 4 bytes
$DVO_Tbl_Ptr_14		2 bytes
$DVO_Tbl_Size_14	1 byte
$DVO_Tbl_14,		$DVO_Tbl_Ptr_14, $DVO_Tbl_Size_14, Offset 0 byte
$LVDS_PnP_ID_Ptr_14	2 bytes
$LVDS_PnP_ID_Size_14	1 byte
$LVDS_PnP_ID_14,	$LVDS_PnP_ID_Ptr_14, $LVDS_PnP_ID_Size_14, Offset 0 byte

$LVDS_Tbl_Ptr_15	2 bytes
$LVDS_Tbl_Size_15	1 byte
$LVDS_Tbl_15,		$LVDS_Tbl_Ptr_15, $LVDS_Tbl_Size_15, Offset 4 bytes
$DVO_Tbl_Ptr_15		2 bytes
$DVO_Tbl_Size_15	1 byte
$DVO_Tbl_15,		$DVO_Tbl_Ptr_15, $DVO_Tbl_Size_15, Offset 0 byte
$LVDS_PnP_ID_Ptr_15	2 bytes
$LVDS_PnP_ID_Size_15	1 byte
$LVDS_PnP_ID_15,	$LVDS_PnP_ID_Ptr_15, $LVDS_PnP_ID_Size_15, Offset 0 byte

$LVDS_Tbl_Ptr_16	2 bytes
$LVDS_Tbl_Size_16	1 byte
$LVDS_Tbl_16,		$LVDS_Tbl_Ptr_16, $LVDS_Tbl_Size_16, Offset 4 bytes
$DVO_Tbl_Ptr_16		2 bytes
$DVO_Tbl_Size_16	1 byte
$DVO_Tbl_16,		$DVO_Tbl_Ptr_16, $DVO_Tbl_Size_16, Offset 0 byte
$LVDS_PnP_ID_Ptr_16	2 bytes
$LVDS_PnP_ID_Size_16	1 byte
$LVDS_PnP_ID_16,	$LVDS_PnP_ID_Ptr_16, $LVDS_PnP_ID_Size_16, Offset 0 byte

$LVDS_Name_Ptr          2 bytes 
$LVDS_Name_Sz           1 byte          ; Skip LFP_PanelName offset and panel name length

;==============================================================================
; Block 42 - Flat Panel Data Tables
;------------------------------------------------------------------------------

SKIP			3 bytes		; Skip block ID and size

			; Flat Panel #1

$Panel_Width_01					2 bytes		; Panel Width
$Panel_Height_01				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither01				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_01		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_01				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_01	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_01				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_01				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #2

$Panel_Width_02					2 bytes		; Panel Width
$Panel_Height_02				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither02				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_02		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_02				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_02	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_02				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_02				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #3

$Panel_Width_03					2 bytes		; Panel Width
$Panel_Height_03				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither03				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_03		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_03				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_03	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_03				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_03				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #4

$Panel_Width_04					2 bytes		; Panel Width
$Panel_Height_04				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither04				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_04		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_04				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_04	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_04				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_04				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #5

$Panel_Width_05					2 bytes		; Panel Width
$Panel_Height_05				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither05				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_05		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_05				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_05	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_05				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_05				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #6

$Panel_Width_06					2 bytes		; Panel Width
$Panel_Height_06				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither06				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_06		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_06				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_06	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_06				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_06				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #7

$Panel_Width_07					2 bytes		; Panel Width
$Panel_Height_07				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither07				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_07		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_07				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_07	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_07				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_07				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #8

$Panel_Width_08					2 bytes		; Panel Width
$Panel_Height_08				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither08				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_08		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_08				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_08	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_08				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_08				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #9

$Panel_Width_09					2 bytes		; Panel Width
$Panel_Height_09				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither09				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_09		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_09				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_09	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_09				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_09				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #10

$Panel_Width_10					2 bytes		; Panel Width
$Panel_Height_10				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither10				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_10		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_10				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_10	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_10				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_10				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #11

$Panel_Width_11					2 bytes		; Panel Width
$Panel_Height_11				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither11				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_11		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_11				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_11	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_11				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_11				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #12

$Panel_Width_12					2 bytes		; Panel Width
$Panel_Height_12				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither12				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_12		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_12				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_12	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_12				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_12				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #13

$Panel_Width_13					2 bytes		; Panel Width
$Panel_Height_13				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither13				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_13		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_13				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_13	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_13				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_13				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #14

$Panel_Width_14					2 bytes		; Panel Width
$Panel_Height_14				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither14				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_14		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_14				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_14	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_14				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_14				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #15

$Panel_Width_15					2 bytes		; Panel Width
$Panel_Height_15				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither15				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_15		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_15				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_15	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_15				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_15				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

			; Flat Panel #16

$Panel_Width_16					2 bytes		; Panel Width
$Panel_Height_16				2 bytes		; Panel Height

SKIP						4 bytes		; Address - 0x0E1180 - Port control
SKIP						3 bytes		; bits[23:0]
SKIP						1 bit		; bit[24]
$Enable_Dither16				1 bit		; Panel #01, 0=No, 1=Yes
SKIP						6 bits		; bits[31:26]
ALIGN

SKIP						4 bytes		; Address - 0x0C7208 - Panel Power on sequencing
$Power_On_Backlight_Enable_Delay_16		13 bits		; Power on Backlight Enable delay
SKIP						3 bits		; bits[15:13]
$PowerUpDelay_16				13 bits		; Power up delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; Address - 0x0C720C - Panel Power off sequencing
$Power_Backlight_Off_Power_Down_Delay_16	13 bits		; Backlight off Power down delay
SKIP						3 bits		; bits[15:13]
$PowerDownDelay_16				13 bits		; Power down delay
SKIP						3 bits		; bits[31:29]
ALIGN

SKIP						4 bytes		; address - 0x0C7210 - Panel Power cycle delay and reference divider
$PowerCycleDelay_16				5 bits		; Power Cycle delay
SKIP						3 bits		; bits[5:7]
ALIGN
SKIP						3 bytes

SKIP						2 bytes 	; 2 bytes at the end

SKIP						18 bytes	; DTD
SKIP						10 bytes	; PnP ID

$Panel_Name_01		13 bytes	; LFP Panel Name
$Panel_Name_02		13 bytes	; LFP Panel Name
$Panel_Name_03		13 bytes	; LFP Panel Name
$Panel_Name_04		13 bytes	; LFP Panel Name
$Panel_Name_05		13 bytes	; LFP Panel Name
$Panel_Name_06		13 bytes	; LFP Panel Name
$Panel_Name_07		13 bytes	; LFP Panel Name
$Panel_Name_08		13 bytes	; LFP Panel Name
$Panel_Name_09		13 bytes	; LFP Panel Name
$Panel_Name_10		13 bytes	; LFP Panel Name
$Panel_Name_11		13 bytes	; LFP Panel Name
$Panel_Name_12		13 bytes	; LFP Panel Name
$Panel_Name_13		13 bytes	; LFP Panel Name
$Panel_Name_14		13 bytes	; LFP Panel Name
$Panel_Name_15		13 bytes	; LFP Panel Name
$Panel_Name_16		13 bytes	; LFP Panel Name

SKIP                     2 bytes        ; EnableScaling
SKIP                    16 bytes        ; Seamless_DRRS_Min_RR
#IF	$Integrated_LVDS == 1 || $eDP == 1	; $Integrated_LVDS == TRUE or eDP == TRUE
  ;==============================================================================
  ; Block 43 - BLC (Backlight Control) Support
  ;------------------------------------------------------------------------------

  SKIP			3  bytes	; Skip block ID and size
  SKIP			1  byte		; Skip row size

        			; Flat Panel #1
  $BLC_Inv_Type_1		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_1	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_1	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_1	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_1	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_1	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_1		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_1	1  byte		; I2C inverter command code

        			; Flat Panel #2
  $BLC_Inv_Type_2		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_2	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_2	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_2	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_2	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_2	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_2		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_2	1  byte		; I2C inverter command code

        			; Flat Panel #3
  $BLC_Inv_Type_3		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_3	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_3	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_3	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_3	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_3	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_3		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_3	1  byte		; I2C inverter command code

        			; Flat Panel #4
  $BLC_Inv_Type_4		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_4	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_4	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_4	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_4	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_4	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_4		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_4	1  byte		; I2C inverter command code

        			; Flat Panel #5
  $BLC_Inv_Type_5		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_5	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_5	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_5	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_5	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_5	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_5		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_5	1  byte		; I2C inverter command code

        			; Flat Panel #6
  $BLC_Inv_Type_6		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_6	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_6	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_6	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_6	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_6	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_6		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_6	1  byte		; I2C inverter command code

        			; Flat Panel #7
  $BLC_Inv_Type_7		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_7	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_7	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_7	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_7	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_7	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_7		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_7	1  byte		; I2C inverter command code

        			; Flat Panel #8
  $BLC_Inv_Type_8		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_8	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_8	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_8	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_8	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_8	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_8		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_8	1  byte		; I2C inverter command code

        			; Flat Panel #9
  $BLC_Inv_Type_9		2  bits		; BLC inverter type
  $BLC_Inv_Polarity_9	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_9	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_9	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_9	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_9	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_9		1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_9	1  byte		; I2C inverter command code

        			; Flat Panel #10
  $BLC_Inv_Type_10    	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_10	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_10	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_10	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_10	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_10	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_10	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_10	1  byte		; I2C inverter command code

        			; Flat Panel #11
  $BLC_Inv_Type_11	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_11	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_11	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_11	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_11	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_11	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_11	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_11	1  byte		; I2C inverter command code

        			; Flat Panel #12
  $BLC_Inv_Type_12	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_12	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_12	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_12	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_12	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_12	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_12	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_12	1  byte		; I2C inverter command code

        			; Flat Panel #13
  $BLC_Inv_Type_13	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_13	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_13	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_13	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_13	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_13	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_13	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_13	1  byte		; I2C inverter command code

        			; Flat Panel #14
  $BLC_Inv_Type_14	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_14	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_14	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_14	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_14	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_14	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_14	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_14	1  byte		; I2C inverter command code

        			; Flat Panel #15
  $BLC_Inv_Type_15    	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_15	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_15	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_15	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_15	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_15	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_15	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_15	1  byte		; I2C inverter command code

        			; Flat Panel #16
  $BLC_Inv_Type_16	2  bits		; BLC inverter type
  $BLC_Inv_Polarity_16	1  bit		; BLC inverter polarity
  $BLC_GPIO_Pins_16	3  bits		; BLC inverter GPIO Pins
  $BLC_GMBus_Speed_16	2  bits		; BLC inverter GMBus speed
  $PWM_Frequency_16	2  bytes	; PWM inverter frequency
  $BLC_Min_Brightness_16	1  byte		; Minimum Brightness, 0 - 255
  $BLC_I2C_Addr_16	1  byte		; I2C inverter Slave address
  $BLC_Brightness_Cmd_16	1  byte		; I2C inverter command code

  
  $POST_BL_Brightness_01	1 byte		; Intial brightness value at POST for Flat Panel #1
  $POST_BL_Brightness_02	1 byte		; Intial brightness value at POST for Flat Panel #2
  $POST_BL_Brightness_03	1 byte		; Intial brightness value at POST for Flat Panel #3
  $POST_BL_Brightness_04	1 byte		; Intial brightness value at POST for Flat Panel #4
  $POST_BL_Brightness_05	1 byte		; Intial brightness value at POST for Flat Panel #5
  $POST_BL_Brightness_06	1 byte		; Intial brightness value at POST for Flat Panel #6
  $POST_BL_Brightness_07	1 byte		; Intial brightness value at POST for Flat Panel #7
  $POST_BL_Brightness_08	1 byte		; Intial brightness value at POST for Flat Panel #8
  $POST_BL_Brightness_09	1 byte		; Intial brightness value at POST for Flat Panel #9
  $POST_BL_Brightness_10	1 byte		; Intial brightness value at POST for Flat Panel #10
  $POST_BL_Brightness_11	1 byte		; Intial brightness value at POST for Flat Panel #11
  $POST_BL_Brightness_12	1 byte		; Intial brightness value at POST for Flat Panel #12
  $POST_BL_Brightness_13	1 byte		; Intial brightness value at POST for Flat Panel #13
  $POST_BL_Brightness_14	1 byte		; Intial brightness value at POST for Flat Panel #14
  $POST_BL_Brightness_15	1 byte		; Intial brightness value at POST for Flat Panel #15
  $POST_BL_Brightness_16	1 byte		; Intial brightness value at POST for Flat Panel #16
#ENDIF	; $Integrated_LVDS == TRUE or eDP == TRUE

;==============================================================================
; Block 44 - BIA (Backlight Image Adaption) Support
;------------------------------------------------------------------------------

SKIP			3  bytes	; Skip block ID and size

SKIP			1 bit			; Reserved
$BIA_Aggress_Level	3  bits	; Power Conservation Preference level
SKIP			3  bits		; Reserved
SKIP			1 bit

$ALS_Response_Data	20  bytes	; ALS Response Data

#IF	0; $eDP == 1	; eDP == TRUE

  ;==============================================================================
  ; Block 45 - BFI (Black Frame Insertion) Support
  ;------------------------------------------------------------------------------

  SKIP			3  bytes	; Skip block ID and size
  SKIP			1  byte		; Skip row size
  
            			; Flat Panel #1
  $BFI_Enable_01		1 bit		; BFI_Enable
  $Brightness_Enable_01	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_01	1 byte		; Brightness percentage in non BFI mode

            			; Flat Panel #2
  $BFI_Enable_02		1 bit		; BFI_Enable
  $Brightness_Enable_02	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_02	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #3
  $BFI_Enable_03		1 bit		; BFI_Enable
  $Brightness_Enable_03	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_03	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #4
  $BFI_Enable_04		1 bit		; BFI_Enable
  $Brightness_Enable_04	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_04	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #5
  $BFI_Enable_05		1 bit		; BFI_Enable
  $Brightness_Enable_05	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_05	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #6
  $BFI_Enable_06		1 bit		; BFI_Enable
  $Brightness_Enable_06	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_06	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #7
  $BFI_Enable_07		1 bit		; BFI_Enable
  $Brightness_Enable_07	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_07	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #8
  $BFI_Enable_08		1 bit		; BFI_Enable
  $Brightness_Enable_08	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_08	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #9
  $BFI_Enable_09		1 bit		; BFI_Enable
  $Brightness_Enable_09	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_09	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #10
  $BFI_Enable_10		1 bit		; BFI_Enable
  $Brightness_Enable_10	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_10	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #11
  $BFI_Enable_11		1 bit		; BFI_Enable
  $Brightness_Enable_11	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_11	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #12
  $BFI_Enable_12		1 bit		; BFI_Enable
  $Brightness_Enable_12	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_12	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #13
  $BFI_Enable_13		1 bit		; BFI_Enable
  $Brightness_Enable_13	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_13	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #14
  $BFI_Enable_14		1 bit		; BFI_Enable
  $Brightness_Enable_14	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_14	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #15
  $BFI_Enable_15		1 bit		; BFI_Enable
  $Brightness_Enable_15	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_15	1 byte		; Brightness % in non BFI mode

            			; Flat Panel #16
  $BFI_Enable_16		1 bit		; BFI_Enable
  $Brightness_Enable_16	1 bit		; Brightness enable in CUI
  SKIP			6 bits		; bits[7:2]
  $Brightness_non_BFI_16	1 byte		; Brightness % in non BFI mode
#ENDIF		; eDP

    ;==============================================================================
    ; Block 46 - Chromaticity  Support
    ;------------------------------------------------------------------------------

    SKIP			3  bytes	; Skip block ID and size


	$Chromacity_Enable_1	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_1    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_1		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_1		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_1			1 byte			; Red x coordinate at 1Bh
	$Red_y_1			1 byte			; Red y coordinate at 1Ch
	$Green_x_1		1 byte			; Green x coordinate at 1Dh
	$Green_y_1		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_1			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_1			1 byte			; Blue y coordinate at 20h
	$White_x_1		1 byte			; White x coordiante at 21h
	$White_y_1		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_2	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_2    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_2		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_2		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_2			1 byte			; Red x coordinate at 1Bh
	$Red_y_2			1 byte			; Red y coordinate at 1Ch
	$Green_x_2		1 byte			; Green x coordinate at 1Dh
	$Green_y_2		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_2			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_2			1 byte			; Blue y coordinate at 20h
	$White_x_2		1 byte			; White x coordiante at 21h
	$White_y_2		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_3	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_3    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_3		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_3		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_3			1 byte			; Red x coordinate at 1Bh
	$Red_y_3			1 byte			; Red y coordinate at 1Ch
	$Green_x_3		1 byte			; Green x coordinate at 1Dh
	$Green_y_3		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_3			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_3			1 byte			; Blue y coordinate at 20h
	$White_x_3		1 byte			; White x coordiante at 21h
	$White_y_3		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_4	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_4    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_4		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_4		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_4			1 byte			; Red x coordinate at 1Bh
	$Red_y_4			1 byte			; Red y coordinate at 1Ch
	$Green_x_4		1 byte			; Green x coordinate at 1Dh
	$Green_y_4		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_4			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_4			1 byte			; Blue y coordinate at 20h
	$White_x_4		1 byte			; White x coordiante at 21h
	$White_y_4		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_5	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_5    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_5		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_5		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_5			1 byte			; Red x coordinate at 1Bh
	$Red_y_5			1 byte			; Red y coordinate at 1Ch
	$Green_x_5		1 byte			; Green x coordinate at 1Dh
	$Green_y_5		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_5			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_5			1 byte			; Blue y coordinate at 20h
	$White_x_5		1 byte			; White x coordiante at 21h
	$White_y_5		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_6	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_6    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_6		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_6		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_6			1 byte			; Red x coordinate at 1Bh
	$Red_y_6			1 byte			; Red y coordinate at 1Ch
	$Green_x_6		1 byte			; Green x coordinate at 1Dh
	$Green_y_6		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_6			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_6			1 byte			; Blue y coordinate at 20h
	$White_x_6		1 byte			; White x coordiante at 21h
	$White_y_6		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_7	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_7    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_7		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_7		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_7		1 byte			; Red x coordinate at 1Bh
	$Red_y_7			1 byte			; Red y coordinate at 1Ch
	$Green_x_7		1 byte			; Green x coordinate at 1Dh
	$Green_y_7		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_7			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_7			1 byte			; Blue y coordinate at 20h
	$White_x_7		1 byte			; White x coordiante at 21h
	$White_y_7		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_8	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_8    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_8		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_8		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_8			1 byte			; Red x coordinate at 1Bh
	$Red_y_8			1 byte			; Red y coordinate at 1Ch
	$Green_x_8		1 byte			; Green x coordinate at 1Dh
	$Green_y_8		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_8			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_8			1 byte			; Blue y coordinate at 20h
	$White_x_8		1 byte			; White x coordiante at 21h
	$White_y_8		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_9	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_9    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_9		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_9		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_9			1 byte			; Red x coordinate at 1Bh
	$Red_y_9			1 byte			; Red y coordinate at 1Ch
	$Green_x_9		1 byte			; Green x coordinate at 1Dh
	$Green_y_9		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_9			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_9			1 byte			; Blue y coordinate at 20h
	$White_x_9		1 byte			; White x coordiante at 21h
	$White_y_9		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_10	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_10    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_10		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_10		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_10			1 byte			; Red x coordinate at 1Bh
	$Red_y_10			1 byte			; Red y coordinate at 1Ch
	$Green_x_10		1 byte			; Green x coordinate at 1Dh
	$Green_y_10		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_10			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_10			1 byte			; Blue y coordinate at 20h
	$White_x_10		1 byte			; White x coordiante at 21h
	$White_y_10		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_11	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_11    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_11		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_11		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_11			1 byte			; Red x coordinate at 1Bh
	$Red_y_11			1 byte			; Red y coordinate at 1Ch
	$Green_x_11		1 byte			; Green x coordinate at 1Dh
	$Green_y_11		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_11			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_11			1 byte			; Blue y coordinate at 20h
	$White_x_11		1 byte			; White x coordiante at 21h
	$White_y_11		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_12	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_12    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_12		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_12		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_12			1 byte			; Red x coordinate at 1Bh
	$Red_y_12			1 byte			; Red y coordinate at 1Ch
	$Green_x_12		1 byte			; Green x coordinate at 1Dh
	$Green_y_12		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_12			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_12			1 byte			; Blue y coordinate at 20h
	$White_x_12		1 byte			; White x coordiante at 21h
	$White_y_12		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_13	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_13    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_13		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_13		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_13			1 byte			; Red x coordinate at 1Bh
	$Red_y_13			1 byte			; Red y coordinate at 1Ch
	$Green_x_13		1 byte			; Green x coordinate at 1Dh
	$Green_y_13		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_13			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_13			1 byte			; Blue y coordinate at 20h
	$White_x_13		1 byte			; White x coordiante at 21h
	$White_y_13		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_14	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_14    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_14		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_14		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_14			1 byte			; Red x coordinate at 1Bh
	$Red_y_14			1 byte			; Red y coordinate at 1Ch
	$Green_x_14		1 byte			; Green x coordinate at 1Dh
	$Green_y_14		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_14			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_14			1 byte			; Blue y coordinate at 20h
	$White_x_14		1 byte			; White x coordiante at 21h
	$White_y_14		1 byte			; White y coordinate at 22h

	$Chromacity_Enable_15	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_15    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_15		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_15		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_15			1 byte			; Red x coordinate at 1Bh
	$Red_y_15			1 byte			; Red y coordinate at 1Ch
	$Green_x_15		1 byte			; Green x coordinate at 1Dh
	$Green_y_15		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_15			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_15			1 byte			; Blue y coordinate at 20h
	$White_x_15		1 byte			; White x coordiante at 21h
	$White_y_15		1 byte			; White y coordinate at 22h


	$Chromacity_Enable_16	1 bit		; enable or disable the chromacity bit 
	$Override_EDID_Data_16    1 bit		; Override the chromaticity bit
	SKIP			6 bits			; Reserved bits
	$Red_Green_16		1 byte			; Red/green chormaticity coordinates at 19h
	$Blue_White_16		1 byte			; Blue/white chromatiity coordinates at 1Ah
	$Red_x_16			1 byte			; Red x coordinate at 1Bh
	$Red_y_16			1 byte			; Red y coordinate at 1Ch
	$Green_x_16		1 byte			; Green x coordinate at 1Dh
	$Green_y_16		1 byte			; Green y ccoordinate at 1Eh
	$Blue_x_16			1 byte			; Blue x coordinate at 1Fh
	$Blue_y_16			1 byte			; Blue y coordinate at 20h
	$White_x_16		1 byte			; White x coordiante at 21h
	$White_y_16		1 byte			; White y coordinate at 22h


EndStruct

;==============================================================================
; List Definitions
;------------------------------------------------------------------------------

List &Chipset_List_Mobile
  Selection	18,	"Sandybridge Mobile"
  Selection	20,	"Ivybridge Mobile"
EndList

List &Chipset_List_Desktop
  Selection	17,	"Sandybridge Desktop"
  Selection	19,	"Ivybridge Desktop"
EndList

List &Chipset_List
  Selection	21,	"Haswell"
  Selection	22,	"Broadwell"
EndList

List &Pwr_Pref_List
  Selection	0x01,	"1 - Maximum Quality with No DPST"
  Selection	0x02,	"2"
  Selection	0x03,	"3"
  Selection	0x04,	"4"
  Selection	0x05,	"5"
  Selection	0x06,	"6 - Maximum Battery"
EndList

List &Cls_After_Signon_List
  Selection	0x00,	"No CLS"
  Selection	0x01,	"0.5 Second Delay + CLS"
  Selection	0x02,	"1.0 Second Delay + CLS"
  Selection	0x03,	"1.5 Second Delay + CLS"
  Selection	0x04,	"2.0 Second Delay + CLS"
  Selection	0x05,	"2.5 Second Delay + CLS"
  Selection	0x06,	"3.0 Second Delay + CLS"
  Selection	0x07,	"3.5 Second Delay + CLS"
EndList

List &Device_Type_List
  Selection	0x0000,	"No Device"

  Selection	0x6001, "Analog CRT - VESA DPMS"  
  Selection	0x6852, "EFP - DVI 1.0 Codec with HotPlug and Power Management"
  Selection	0x6853, "EFP - DVI-I (Analog & Digital Connector)"
  Selection	0x5062, "LFP - LVDS with Power Management"

  ;	Selection	0x0609, "Analog TV - Composite and S-Video Out" 
  ;	Selection	0x4001, "Analog CRT - VESA DPMS & Hot Plug"
  ;	Selection	0x0209, "Analog TV - Composite Video Out"
  ;	Selection	0x0289, "Analog TV - Macrovison"
  ;	Selection	0x020C, "Analog TV - RF Tuner and Composite Video Out"
  ;	Selection	0x0209, "Analog TV - SCART Video Connector"
  ;	Selection	0x6009, "Analog TV - Codec supported HotPlug and Power Management"     
  ;	Selection	0x6152, "EFP - Dual Channel DVI-D"
  ;	Selection	0x60D2, "EFP - DVI-D & HDCP"
  ;	Selection	0x6062, "OpenLDI with HotPlug and Power Management"
  ;	Selection	0x6162, "OpenLDI with DualPixel Support"
  ;	Selection	0x5012, "LFP - PanelLink"
  ;	Selection	0x5042, "LFP - CMOS with Power Management"
  ;	Selection	0x5162, "LFP - Dual-Channel LVDS"
  ;	Selection	0x51E2, "LFP - Dual-Channel LVDS with HDCP"
  ;	Selection	0xF0D2, "Integrated HDMI"
  ;	Selection	0x60D2, "HDMI - Hotplug and Power Management"
  
EndList

;List &Int_EFP_Device_Type_List
;        Selection       0x0000, "No Device"
;        Selection       0x2, "Integrated DisplayPort Only"
;        Selection       0x7, "Integrated DisplayPort with HDMI/DVI Compatible"
;        Selection       0x6, "Integrated DisplayPort with DVI Compatible"
;        Selection       0x5, "Integrated HDMI/DVI"
;        Selection       0x4, "Integrated DVI Only"
;EndList

; This is the new list for the selection of the Device Class

List &Int_EFP_Device_Type_List
        Selection       0x0000, "No Device"
        Selection       0x68C6, "Integrated DisplayPort Only"
        Selection       0x60D6, "Integrated DisplayPort with HDMI/DVI Compatible"
        Selection       0x68D6, "Integrated DisplayPort with DVI Compatible"
        Selection       0x60D2, "Integrated HDMI/DVI"
        Selection       0x68D2, "Integrated DVI Only"
EndList

List &Disabled_Enabled_List
  Selection	0,	"Disabled"
  Selection	1,	"Enabled"
EndList

List &VBIOS_Post_Mode_List
  Selection	0x00,	"Skip mode-set during VBIOS POST"
  Selection	0x03,	"03h"
  Selection	0x12,	"12h"
  Selection	0x13,	"13h"
  Selection	0x30,	"30h"
  Selection	0x32,	"32h"
  Selection	0x34,	"34h"
  Selection	0x40,	"40h"
  Selection	0x41,	"41h"
  Selection	0x42,	"42h"
  Selection	0x43,	"43h"
  Selection	0x44,	"44h"
  Selection	0x45,	"45h"
  Selection	0x50,	"50h"
  Selection	0x52,	"52h"
  Selection	0x54,	"54h"
EndList

List &DVO_Port_List
  Selection	0x00,	"N/A"
  Selection	0x01,	"DVO_B"
EndList			 

List &Int_EFP_Port_List
  Selection	0x00,	"N/A"
  Selection	0x01,	"HDMI-B"
  Selection	0x02,	"HDMI-C"
  Selection 	0x03,	"HDMI-D"
  Selection	0x07,	"DisplayPort-B"
  Selection	0x08,	"DisplayPort-C"
  Selection	0x09,	"DisplayPort-D"
EndList			 

List &eDP_Port_List
  Selection	0x0a,	"DisplayPort-A"
  Selection	0x09,	"DisplayPort-D"
EndList			 

List &Int_EFP_Connector_Info
  Selection	0x00,	"N/A"
  Selection	0x01,	"HDMI Certified"
  Selection	0x02,	"DisplayPort"
  Selection	0x03,	"DVI"
EndList			 

List &Int_DP_AUX_Channel_List
  Selection	0x00,	"N/A"
  Selection	0x10,	"DisplayPort-B AUX Channel"
  Selection	0x20,	"DisplayPort-C AUX Channel"
  Selection	0x30,	"DisplayPort-D AUX Channel"
EndList			 

List &Int_eDP_AUX_Channel_List
  Selection	0x40,	"DisplayPort-A AUX Channel"
  Selection	0x30,	"DisplayPort-D AUX Channel"
EndList

List &GPIO_Pin_List
  Selection	0x00,	"N/A"
  Selection	0x05,	"Integrated HDMI-B DDC GPIO Pins / sDVO I2C GPIO pins"
  Selection	0x04,	"Integrated HDMI-C DDC GPIO Pins"
  Selection	0x06,	"Integrated HDMI-D DDC GPIO Pins"
  Selection	0x01,	"I2C GPIO pins"
  Selection	0x02,	"Analog CRT DDC GPIO pins"
  ;  Selection	0x03,	"Integrated LVDS DDC GPIO pins"
  ;  Selection	0x1D,	"SDVO DDC1 GPIO pins"
  ;  Selection	0x2D,	"SDVO DDC2 GPIO pins"
EndList			 

List &SDVO_GPIO_Pin_List
  Selection	0x00,	"N/A"
  Selection	0x05,	"sDVO I2C GPIO pins"
  Selection	0x01,	"I2C GPIO pins"
  Selection	0x02,	"Analog CRT DDC GPIO pins"
  ;  Selection	0x03,	"Integrated LVDS DDC GPIO pins"
  ;  Selection	0x1D,	"SDVO DDC1 GPIO pins"
  ;  Selection	0x2D,	"SDVO DDC2 GPIO pins"
EndList	

List &GMBus_Speed_List
  Selection	0x01,	"50 KHz"
  Selection	0x00,	"100 KHz"
  Selection	0x02,	"400 KHz"
  Selection	0x03,	"1 MHz"
EndList			 

List &FDI_Rx_Pol_List
  Selection	0x00,	"Normal"
  Selection	0x01,	"Inverted"
EndList

List &IntSys_List
  Selection	0x00,	"Disabled"
  Selection	0x01,	"USE INT 15H"
EndList

List &Inv_Type_List
  Selection	0x00,	"None/External"
  Selection	0x02,	"PWM"
EndList

List &Inv_Polarity_List
  Selection	0x00,	"Normal"
  Selection	0x01,	"Inverted"
EndList

List &IntXXh_List
  Selection	0x00,	"Disabled"
  Selection	0x01,	"Use Interrupt 15h"
EndList

List &LVDS_Channel_List
  Selection	0x00,	"Single Channel"
  Selection	0x01,	"Dual Channel"
EndList

List &INT_LVDS_Channel_List
  Selection	0x00,	"Automatic Selection"
  Selection	0x01,	"Single Channel"
  Selection	0x02,	"Dual Channel"
EndList

List &LVDS_Config_List
  Selection	0x00,	"No Local Flat Panel"
  Selection	0x03,	"eDP (LFP Driven by Int-DisplayPort Encoder)"
EndList

List &No_Yes_List
  Selection	0,	"No"
  Selection	1,	"Yes"
EndList

List &Yes_No_List
  Selection	0,	"Yes"
  Selection	1,	"No"
EndList

List &Off_On_List
  Selection	0,	"Off"
  Selection	1,	"On"
EndList

List &OS_Driver_List
  Selection	0,	"OS Default Algorithm"
  Selection	1,	"Driver Algorithm"
EndList

List &OS_DriverP_List
  Selection	0,	"OS Default Algorithm"
  Selection	1,	"Driver Persistence Algorithm"
EndList

List &Panel_Color_Depth_List
  Selection	0x00,	"18-bit Color Depth"
  Selection	0x01,	"24-bit Color Depth"
EndList

List &eDP_Panel_Color_Depth_List
  Selection	0x00,	"18-bit Color Depth"
  Selection	0x01,	"24-bit Color Depth"
  Selection	0x02,	"30-bit Color Depth"
  Selection	0x03,	"36-bit Color Depth"
EndList

List &eDP_VSwing_Preemph_table_List
    Selection    0x00,    "Low Power VSwing/Pre-Emphasis Table"
    Selection    0x01,    "Default VSwing/Pre-Emphasis Table"
EndList

List &eDP_Link_DataRate_List
  Selection	0x0,	"1.62 Gbps"
  Selection	0x1,	"2.70 Gbps"
  Selection 0x2, "5.40 Gbps"
EndList

List &eDP_Link_LaneCount_List
  Selection	0x00,	"x1"
  Selection	0x01,	"x2"
  Selection	0x03,	"x4"
EndList

List &DP_Link_PreEmp_List
  Selection	0x00,	"Level-0" 
  Selection	0x01,	"Level-1" 
  Selection	0x02,	"Level-2" 
  Selection	0x03,	"Level-3" 
EndList

List &DP_EDP_Link_VSwing_List
  Selection	0x00,	"Level-0" 
  Selection	0x01,	"Level-1" 
  Selection	0x02,	"Level-2"
EndList


List &Panel_Connector_List
  Selection	0x00,	"SPGW"
  Selection	0x01,	"OpenLDI"
EndList

List &Panel_List
  Selection	0x00,	"PANEL #01"
  Selection	0x01,	"PANEL #02"
  Selection	0x02,	"PANEL #03"
  Selection	0x03,	"PANEL #04"
  Selection	0x04,	"PANEL #05"
  Selection	0x05,	"PANEL #06"
  Selection	0x06,	"PANEL #07"
  Selection	0x07,	"PANEL #08"
  Selection	0x08,	"PANEL #09"
  Selection	0x09,	"PANEL #10"
  Selection	0x0A,	"PANEL #11"
  Selection	0x0B,	"PANEL #12"
  Selection	0x0C,	"PANEL #13"
  Selection	0x0D,	"PANEL #14"
  Selection	0x0E,	"PANEL #15"
  Selection	0x0F,	"PANEL #16"
EndList

;List &Panel_Stretch_List
;  Selection	0x00,	"Disable Panel Fitting"
;  Selection	0x01,	"Enabled for Text Modes Only"
;  Selection	0x02,	"Enabled for Graphics Modes Only"
;  Selection	0x03,	"Enabled for Both Text and Graphics Modes"
;EndList

List &Panel_Stretch_List
  Selection	0x03,	"Full screen"
  Selection	0x02,	"Maintain aspect ratio (letterbox/pilar box)"
  Selection	0x01,	"Centering (Not applicable for VGA modes)"
EndList

List &PCI_BIOS_Disabled_Enabled_List
  Selection	0x00,	"Disabled"
  Selection	0x01,	"Resize to 0.5K boundary"
  Selection	0x20,	"Resize to 16K boundary"
EndList

List &RelStage
  Selection	1,	"Production"
  Selection	254,	"Evaluation"
EndList

List &SSC_List      
  Selection	0,	"120 MHz"
EndList

List &SDVO_Panel_List
  Selection	0x00,	"PANEL #01"
  Selection	0x01,	"PANEL #02"
  Selection	0x02,	"PANEL #03"
  Selection	0x03,	"PANEL #04"
EndList

List &Sprite_Display_List
  Selection	0,	"Secondary Display"
  Selection	1,	"Primary Display"
EndList

List &Under_Over_List
  Selection	0x0,	"Enable Underscan and Overscan modes"
  Selection	0x1,	"Enable only overscan modes"
  Selection	0x2,	"Enable only underscan modes"
EndList

List &Inter_Exter_List
  Selection	0,	"External Termination"
  Selection	1,	"Internal Termination"
EndList

List &DPS_Panel_Type_List
  Selection       0x00,    "Static DRRS"
  Selection       0x02,    "Seamless"
EndList

List &MSA_TimingDelay_List
  Selection       0x00,    "Line 1"
  Selection       0x01,    "Line 2"
  Selection       0x02,    "Line 3"
  Selection	0x03,	 "Line 4"
EndList

List &Blt_Control_Type_List
  ;Selection       0x00,    "Default"
  Selection       0x01,    "CCFL Backlight"
  Selection       0x02,    "LED Backlight"
EndList

List &Display_Clk_Control_Type_List
  Selection       0x00,    "DCI mode (Display Clock Integration mode)"
  Selection       0x01,    "BT Mode (legacy Buffer Through Mode)"
EndList

List &Panel_Timings_List
  Selection	0x00,	"Preferred"
  Selection	0x01,	"Best fit"
EndList

List &Hdmi_Haswell_Broadwell_LS_List
  Selection	0x00,	"400mV 0.0dB Cost Reduced Level Shifter (HSW and BDW)"
  Selection 0x01,	"400mV 2.0dB Cost Reduced Level Shifter (HSW only)"
  Selection	0x02,	"400mV 3.5dB Cost Reduced Level Shifter (HSW and BDW)"
  Selection	0x0C,	"400mV 6.0dB Cost Reduced Level Shifter (BDW only)"
  Selection	0x0D,	"450mV 0.0dB Cost Reduced Level Shifter (BDW only)"
  Selection	0x03,	"600mV 0.0dB Cost Reduced Level Shifter (HSW and BDW)"
  Selection	0x04,	"600mV 2.0dB Cost Reduced Level Shifter (HSW only)"
  Selection	0x0E,	"600mV 2.5dB Cost Reduced Level Shifter (BDW only)"
  Selection	0x05,	"600mV 3.5dB Cost Reduced Level Shifter (HSW only)"
  Selection	0x0F,	"600mV 4.5dB Active Level Shifter/Cost Reduced Level Shifter (BDW only)"
  Selection	0x06,	"800mV 0.0dB Active Level Shifter/Cost Reduced Level Shifter (HSW and BDW)"
  Selection	0x07,	"800mV 2.0dB Cost Reduced Level Shifter (HSW and BDW)"
  Selection 0x08,	"850mV 0.0dB Cost Reduced Level Shifter (HSW only)"
  Selection 0x09,	"900mV 0.0dB Cost Reduced Level Shifter (HSW only)"
  Selection 0x0A,	"950mV 0.0dB Cost Reduced Level Shifter (HSW only)"
  Selection 0x0B,	"1000mV 0.0dB Cost Reduced Level Shifter (HSW and BDW)"
EndList

List &DisplayList
  Selection       0x08, "LFP"
  Selection       0x01, "CRT"
  Selection       0x04, "EFP"
  Selection       0x40, "EFP2"
  Selection       0x20, "EFP3"
  Selection       0x00, "None"        
EndList

List &wait_line_link
   Selection	0x00,	"0 lines to wait"
   Selection	0x01,	"2 lines to wait"
   Selection	0x02,	"4 lines to wait"
   Selection	0x03,	"8 lines to wait"
EndList  

;==============================================================================
; Page Definitions
;------------------------------------------------------------------------------

BeginInfoBlock
PPVer	"3.00"
Image EOF Thru EOF At EOF
EndInfoBlock

;==============================================================================
; Page - Revision History
;------------------------------------------------------------------------------

Page "VBT Information "

  
  Title   "PLATFORM : Haswell/Broadwell"

  Title   "VBT version: 189"

#IF	$LVDS_Config == 3
  Title   "Supported LFP type: eDP"
#ELSE
  Title   "Supported LFP type: No LFP"
#ENDIF

  ;	Title	"The Format for the Item in Revision History:" 
  ; 
  ;	Title	" DD-MM-YY:  Describe the BMP feature revisions. To allow revision" 
  ;	Title	"            notes to be seen with smaller display modes, the length"
  ;	Title	"            of each line must be restricted to the length of the"
  ;	Title	"            dashed line below. The key words [Add] [Delet] [Update]" 
  ;	Title	"            have to be used in the description."
  ;

  ;	Title	"The List of Revision History:"
  ;
  ;	Title	"|------------- Maximum Length of revision note. ------------------------------------------------------------|"

 ; TitleB "Information"
;  Title   " 06-06-11:  Merging HSW Code changes to main"
; Title   " 01-20-11:  Added option for Intial brightness at POST for LFP."
;  Title   " 01-20-11:  Added S3D enable/Disable VBT bit."
;  Title   " 06-10-09:  Merging SNB Code changes to main and added MSA feature for SNB."
;  Title   " 04-06-09:  Enabled eDP on Port D for Switchable Gfx and for Mobile PCH for AIO designs."
;  Title   " 06-08-08:  Added DPS_Panel_Type field in Block #40 to distinguish between SDRRS and DRRS panels."

EndPage		; Revision History


;==============================================================================
; Page - General platform Configuration
;------------------------------------------------------------------------------

Page "General platform Configuration"

  Combo	$FDI_RX_POL, " FDI Rx Polarity for LPT:", &Inv_Polarity_List,
  Help	"This setting is to configure the FDI Rx Polarity on PCH side . "

  Combo	$Embedded_Platform, "Embedded Platform:", &No_Yes_List,
  Help	"This feature allows a selectable option to determine whether "
  "the platform is embedded design or not.\r\n"
  
  
  Combo	$bmp_Dynamic_CdClock_Supported, "Dynamic CD Clock Support: ", &Disabled_Enabled_List,
  Help	"This feature is applicable only for Broadwell. \n"
  "Enabling this feature configures optimal CD Clock frequency at run time .\n "
  
  
EndPage		; General platform Configuration

;==============================================================================
; Page - UEFI GOP Driver Configuration
;------------------------------------------------------------------------------

Page "UEFI GOP Driver Configuration"

Combo	$Hotplug_Support_Enb, " Hot Plug Support:", &Disabled_Enabled_List,
Help	"This feature is to enable/disable Hot Plug Support for displays in pre-boot environment. This is not applicable in Graphics Driver mode. "
  
  
  Title   "Child Device Configuration"    
  Link    "Child Device List", "Child Device List"
  ;==============================================================================
  ; Page - Boot Display Algorithm
  ;------------------------------------------------------------------------------

  Page "Child Device List"
    
    Title   "A child device is a combination of one or more displays. Select the child devices that the GOP driver should enumerate if detected" 
    Title   "Note: The child devices are listed here in decreasing order of priority. In case the system BIOS does not specify the child device to start, then GOP driver selects the highest priority child device" 
    
    Title   "Child Device 1"
    Combo   $ChildDevice1Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice1Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"

    Title   " "
    Title   "Child Device 2"
    Combo   $ChildDevice2Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice2Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 3"
    Combo   $ChildDevice3Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice3Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 4"
    Combo   $ChildDevice4Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice4Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 5"
    Combo   $ChildDevice5Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice5Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 6"
    Combo   $ChildDevice6Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice6Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 7"
    Combo   $ChildDevice7Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice7Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 8"
    Combo   $ChildDevice8Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice8Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 9"
    Combo   $ChildDevice9Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice9Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 10"
    Combo   $ChildDevice10Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice10Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 11"
    Combo   $ChildDevice11Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice11Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 12"
    Combo   $ChildDevice12Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice12Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 13"
    Combo   $ChildDevice13Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice13Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 14"
    Combo   $ChildDevice14Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice14Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 15"
    Combo   $ChildDevice15Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice15Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
    
    Title   " "
    Title   "Child Device 16"
    Combo   $ChildDevice16Primary, " Primary display: " , &DisplayList,
    Help    "Primary Display\r\n"
    Combo   $ChildDevice16Secondary, " Secondary display: " , &DisplayList,
    Help    "Secondary Display\r\n"
  EndPage    ;"Child Device List"
EndPage    ; "UEFI GOP Driver Configuration"

#IF 0
;==============================================================================
; Page - Legacy VBIOS configuration
;------------------------------------------------------------------------------

Page "Legacy VBIOS Configuration"

  Link	"Sign-on Message Options", "Sign-on Message Options "
  Link  "General Video BIOS Features", "General Video BIOS Features"    
  Link  "Boot Display Algorithm ", "Boot Display Algorithm "
  Link  "System BIOS Hooks ", "System BIOS Hooks "

  ;==============================================================================
  ; Page - Message options
  ;------------------------------------------------------------------------------

  Page "Sign-on Message Options "

    Link	"Close Table" , ".."
   ; Title	"This BMP Script is used for:" 
   ; Title	"	Video BIOS Build:  1000"
   ; Title	"	Video BIOS Baseline:  PC14.8"
   ; Title	"	BMP Application Version:  PC1.5"

    Title	"Five lines of signon message, maximum of 155 characters"

    MultiText $Signon, "  Video BIOS 'signon' message:", 
    Help	"This feature defines the signon message that will be "
    "displayed at the end of video BIOS POST. when the machine is "
    "booted.  You may enter a maximum of five lines of text, with "
    "no more than 70 characters on each line, and no more than "
    "155 total characters."

    Title	"Display Options"

    Combo	$Msg_Enable, "  Enable signon messages:", &No_Yes_List,
    Help	"'YES' will enable the signon message, copyright message, "
    "eval message, and requested delay.\r\n"
    "\r\n"
    "'NO' will disable showing of the signon messages."

    Combo	$Cls_After_Signon, "  Clear screen after signon:", &Cls_After_Signon_List,
    Help	"This feature allows a selectable option to clear display "
    "after video BIOS signon or leave the signon on the display."
    "\r\n"
    "\r\n"
    "Setting this field to anything other than 'No CLS' will "
    "cause the video BIOS to pause for the specified number of "
    "seconds while displaying the signon and copyright messages."
    "\r\n"
    "The default is 'No CLS', which causes the BIOS to display "
    "the signon messages and continue without pausing or clearing "
    "the screen."
    
  EndPage		; Message Options

  ;============================================================================
  ; Page - General Video BIOS Features
  ;----------------------------------------------------------------------------

  Page "General Video BIOS Features"

    Link	"Close Table" , ".."
    Title	"General Video BIOS Features"

    Combo	$bmp_VBIOS_Post_Mode, "  VBIOS POST mode resolution:", &VBIOS_Post_Mode_List,
    Help	"This option selects the mode resolution that will be set "
    "in Video BIOS POST to display sign on message. Default mode is 03h.\r\n"
    "\r\n"
    "Modes:\r\n"
    "  03h - 720 x 400 x text\r\n"
    "  12h - 640 x 480 x 4 bpp\r\n"
    "  13h - 320 x 200 x 8 bpp\r\n"
    "  30h - 640 x 480 x 8 bpp\r\n"
    "  32h - 800 x 600 x 8 bpp\r\n"
    "  34h - 1024 x 768 x 8 bpp\r\n"
    "  41h - 640 x 480 x 16 bpp\r\n"
    "  43h - 800 x 600 x 16 bpp\r\n"
    "  45h - 1024 x 768 x 16 bpp\r\n"
    "  50h - 640 x 480 x 32 bpp\r\n"
    "  52h - 800 x 600 x 32 bpp\r\n"
    "  54h - 1024 x 768 x 32 bpp"

    ;    Combo	$bmp_Resize_PCI_BIOS, "  Resize PCI BIOS:", &PCI_BIOS_Disabled_Enabled_List,
    ;    Help	"This feature, when enabled, will resize the run time video "
    ;    "BIOS using the selected granularity.  Resizing will remove "
    ;    "or add padding (end of video BIOS is set to '0') after the "
    ;    "last line of real code.  In some cases, code that is not "
    ;    "needed for reposting will also be removed.\r\n"
    ;    "\r\n"
    ;    "Note: This is a PCI feature where an option ROM may resize "
    ;    "itself by adjusting the option ROM size byte (at offset "
    ;    "C000h:0002h) during that option ROM's POST execution.  A new "
    ;    "checksum is also calculated."

    Combo	$DPMS_AIM_Bit, "  VESA VBE/PM Affects all Display Devices:", &No_Yes_List,
    Help	"This feature allows the VESA VBE \ PM functions to affect "
    "all displays instead of just the CRT.\r\n"
    "\r\n"
    "Note:  The VESA VBE / PM specification was developed for CRT "
    "only (except for reduced on which is not supported).  This "
    "feature allows the 'on', 'standby', 'suspend', and 'off' "
    "state to affect the other displays in an appropriate as "
    "possible way.  Since the original spec was written for CRT "
    "only activating this feature is not VESA compliant."

              			; Do not remove the following. Commented out due to 
              			; legal issue.

    ;	Combo	$DPMS_ACPI_Bit, "  Limit DPMS supported Power states:", &No_Yes_List,
    ;	Help	"Feature to limit DPMS supported states by redefining the "
    ;		"VESA VBE / PM 'standby' and 'suspend' states to be equal to "
    ;		"the DPMS 'Off' state (horizontal and vertical syncs off).  "
    ;		"Since this deviates from the VESA VBE/PM and DPMS specs it "
    ;		"is not VESA compatible."

    ;    #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
    ;      Combo	$Enable_LFPOn_Override, "  LFP 'on' overridden by Function 5F64h, 08h:", &No_Yes_List,
    ;      Help	"This feature when enabled, LFP can only be set to Power state 'ON' "
    ;      "through Intel VBIOS function 5F64h, sub-function 08h.  VESA/PM function 4F10h "
    ;      "(sub-function 01h) or Intel VBIOS function 5F64h, sub-function 00h can not "
    ;      "Power 'ON' the LFP."
    ;    #ENDIF	; $Integrated_LVDS == 1	; $Integrated_LVDS == TRUE

          			; Do not remove the following. For special application.

    ;	Combo	$Skip_Boot_CRT_Detect, "  Skip CRT Detect during Boot:", &No_Yes_List,
    ;	Help	"This feature allows user to skip CRT detection during Boot. "
    ;		"If yes, VBIOS will allow boot to CRT display even though the CRT "
    ;		"display is not attached."

    
    Combo	$Allow_Boot_DVI, "  Allow Boot Display to DVI even if DVI is not attached", &No_Yes_List,
    Help	"When Enabled : this feature allows a DVI display to "
    "successfully be used as a Boot Display Device when not attached.\r\n"
    "If the DVI display is not attached, VBIOS shall boot to the DVI "
    "display device using 640x480@60Hz timings.\r\n"
    "When Disabled : it is required for the DVI display to be attached "
    "in order for it to be used as a Boot Display Device."
    
    Combo	$Enable_Panel_Fitting, "  Display scaling:", &Panel_Stretch_List,
    Help	"This feature allows a selectable option for various display scaling features for LFP panels "
    "Full screen, Centering and Maintain Aspect ratio are the available options\r\n"
    "Note, this initial state is overridden by the panel fitting hook (5F34h)."

    ;    Combo	$Allow_Aspect_Ratio, "  Preserve Aspect Ratio(DOS)", &Disabled_Enabled_List,
    ;    Help	"When this feature is enabled, the Video BIOS will preserve the aspect ratio. "
    ;    "When this feature is disabled, the Video BIOS will not preserve the aspect"
    ;    "ratio but display the screen in full screen mode.\r\n\r\n"
    ;    "Note: This feature is only used when the Video BIOS is the sole component"
    ;    "driving the display. When the Graphics Driver is loaded, the Graphics Driver"
    ;    "will determine based on other VBT bits as well as the end user selection"
    ;    "in CUI the Aspect settings"

    ;    Combo	$Override_VGA_720p, "  Underscan 480p modes using 720p timing", &No_Yes_List,
    ;    Help	"When Enabled : this feature shall use 720p timing for all VGA and 480p modes "
    ;    "if the HDMI display device has support for 720p timing. Otherwise, VBIOS shall "
    ;    "use display preferred timing.\r\n"

    Combo	$Hotplug_Support_Enb, " Hot Plug Support in DOS:", &Disabled_Enabled_List,
    Help	"This feature is to enable/disable Hot Plug Suppport in DOS for CRT/DP/HDMI displays "

    Combo	$Enable_Panel_Timing, " Select Panel Timing Algorithm:", &Panel_Timings_List,
    Help	"Select between a best fit and preferred panel timing algorithm."
    "The best fit algorithm checks all resolutions in a panel's EDID "
    "(i.e. established, standard, and DTD timing sections) to see if one "
    "matches the currently requested resolution and then uses that resolution."
    " The preferred algorithm always uses the panel's preferred timings (i.e. "
    "fist DTD in EDID) and fits the current mode to that resolution. "
    "By selecting preferred mode, mode-sets will be quicker on integratd DP and HDMI panels"
  EndPage		; General Video BIOS Features

  ;==============================================================================
  ; Page - Boot Display Algorithm
  ;------------------------------------------------------------------------------

  Page "Boot Display Algorithm "

    Link	"Close Table" , ".."
    Table	$Dev_Boot_Table " Display Device Boot Table",
    Column "Devices Attached" , 1 byte , BIN 
    Column "Primary display(VGA)" , 1 byte , BIN
    Column "Secondary display" , 1 byte , BIN,
    Help	"This feature allows a configurable table for video BIOS POST boot up display device.\r\n"
    "\r\n"
    "If the displays in the 'Devices Attached' column are detected, the video BIOS will boot to the display combination\r\n"
    "given in the Primary display(VGA) column and Secondary display column.  The bit pattern for either column is as\r\n"
    "follows:\r\n"
    "\r\n"
    "Bit:        7          \t6          5          4          3        2         1     \t0   \r\n"
    "           Reserved    EFP2    EFP3    CRT2    LFP    EFP    Reserved     CRT  \r\n"
    "\r\n"
    "Using the primary and secondary display combination, CLONE mode or TWIN mode can be set. To set CLONE mode, only\r\n" 
    "one device should be selected in primary and secondary display column each. The video BIOS POST boot up will be \r\n"
    "displayed in both the devices selected in primary and secondary display column.\r\n"
    "\r\n"
    "In TWIN mode, two display devices can be selected in the single column (either primary or secondary). Only CRT and\r\n"
    "LVDS can be set in TWIN mode.\r\n"
    "\r\n"
    "Some examples:\r\n"
    "\tDB 00001001, 00000001, 00001000		; LFP+CRT  CRT on primary, LFP on secondary\r\n"
    "\tDB 00001101, 00001001, 00000100		; LFP+CRT  LFP+CRT on primary, EFP on secondary\r\n"
    "\r\n"
    "Note: Primay display column cannot be left empty. VGA modes will be displayed only on devices selected in primary \r\n"
    "          display column.\r\n"
    "Note: This table is skipped when a valid display combination is returned by the 5F35h (Boot Display) system BIOS hook.\r\n    "
  EndPage		; Boot Display Algorithm
  ;==============================================================================
  ; Page - System BIOS Hooks
  ;------------------------------------------------------------------------------

  Page "System BIOS Hooks "

    Link	"Close Table" , ".."
                			; Do not remove.  For special application.
    
    ;	Combo	$H14_Update_Display, "5F14h - Update Expansion/Display State:", &IntXXh_List, 
    ;	Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;		"BIOS will call the interrupt 15h, 5F14h, 078Dh hook, as specified "
    ;		"in the video BIOS reference guide, at the end of video BIOS "
    ;		"POST.  When disabled, 5F14h, 078Dh will not be called."

    Combo	$H14_Get_Misc_Status, "5F14h - Get Miscellaneous Status (Mobile only)", &IntXXh_List, 
    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    "BIOS will call the interrupt 15h, 5F14h, 078Fh hook, as specified "
    "in the video BIOS reference guide, at the end of video BIOS "
    "POST.  When disabled, 5F14h, 078Fh will not be called.\r\n\r\n"
    "Note: This hook is required for DP Redriver feature to work in mobile platform."

    ;    Combo	$H31_POST_End_Hook, "5F31h - POST Completion Hook:", &IntXXh_List, 
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F31h hook, as specified "
    ;    "in the video BIOS reference guide, at the end of video BIOS "
    ;    "POST.  When disabled, 5F31h will not be called."

    ;    Combo	$H33_After_Mode_Set, "5F33h - Hook After Mode Set:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F33h hook, as specified "
    ;    "in the video BIOS reference guide, at the end of set mode.  "
    ;    "When disabled, 5F33h will not be called."

    Combo	$H34_Set_LFP_Fitting, "5F34h - Set Panel Fitting Hook ", &IntXXh_List,
    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    "BIOS will call the interrupt 15h, 5F34h hook ,as specified "
    "in the video BIOS reference guide, in the middle of video "
    "BIOS POST.  The returned value will override the default BMP "
    "setting.  When disabled, 5F34h will not be called."

    Combo	$H35_Bootup_Display, "5F35h - Boot Up Display Devices Hook:", &IntXXh_List,
    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    "BIOS will call the interrupt 15h, 5F35h hook, as specified "
    "in the video BIOS reference guide, in the middle of video "
    "BIOS POST.  When disabled, 5F35h will not be called.\r\n"
    "\r\n"
    "Note, Enabling this hook and returning a good display"
    "combination will override the 'Boot Display Algorithm' "
    "table."

    ;    Combo	$H36_Boot_TV_Format, "5F36h - Boot TV Format Hook:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F36h hook, as specified "
    ;    "in the video BIOS reference guide, in the middle of video "
    ;    "BIOS POST.  When disabled, 5F36h will not be called."

    ;    Combo	$H38_Before_Mode_Set, "5F38h - Hook Before Mode Set:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F38h hook, as specified "
    ;    "in the video BIOS reference guide, at the beginning of set "
    ;    "mode.  When disabled, 5F38h will not be called."

    Combo	$H40_Set_Panel_Type, "5F40h - Panel Type Hook:", &IntXXh_List,
    Help	"This feature when enabled (Use interrupt 15h) allows the "
    "system BIOS to return the panel type to be used in booting "
    "the system and from then on by both the video BIOS and "
    "driver.  If disabled, the BMPed panel type will be used."

    ;    Combo	$H45_VESA_DDC_Hook, "5F45h - Hook Before VESA VBE/DDC:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F45h hook, as specified "
    ;    "in the video BIOS reference guide, before the DDC functions "
    ;    "are dispatched.  This allows the video BIOS DDC functions to "
    ;    "be taken over.  When disabled, 5F45h will not be called."

    ;    Combo	$H46_VESA_PM_Hook, "5F46h - Hook Before VESA VBE/PM:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F46h hook, as specified "
    ;    "in the video BIOS reference guide, before the PM functions "
    ;    "are dispatched.  This will allow the PM functions to be "
    ;    "taken over or for custom setup.  When disabled, 5F46h will "
    ;    "not be called."

    ;    Combo	$H47_Notify_Display_Sw, "5F47h - Notify Display Switch Hook:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F47h hook, as specified "
    ;    "in the video BIOS reference guide, after a new display "
    ;    "combination has been set by the video BIOS.  When disabled, "
    ;    "5F47h will not be called."

    ;    Combo	$H48_After_VESA_PM, "5F48h - Hook After VESA VBE/PM Set Power State:", &IntXXh_List,
    ;    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    ;    "BIOS will call the interrupt 15h, 5F48h hook, as specified "
    ;    "in the video BIOS reference guide, after the PM functions "
    ;    "have been executed.  This allows and custom setup to be "
    ;    "reset.  When disabled, 5F48h will not be called."

    Combo	$H49_Get_BL_Inv_Pol, "5F49h - Hook to get the backlight inverter type, polarity and initial brightness:", &IntXXh_List,
    Help	"When this feature is enabled (Use Interrupt 15h), the video "
    "BIOS will call the interrupt 15h, 5F49h hook, as specified "
    "in the video BIOS reference guide, to get the backlight inverter type, "
    "polarity information and initial brightness.  When disabled, 5F49h will not be called."

    Combo	$H51_LFP_Panel_Type, "5F51h - Hook to get LVDS type from Setup:", &IntXXh_List,
    Help 	"When this feature is enabled (Use Interrupt 15h), the video "
    "BIOS will call the interrupt 15h, 5F51h hook, as specified "
    "in the video BIOS reference guide, to get the Panel Type i.e. 'No Panel', 'Int LVDS' "
    "'SDVO LVDS' or 'eDP'.  When disabled, 5F51h will not be called."

    Combo 	$H52_LFP_Panel_Color_Depth, "5F52h - Hook to get Panel Color Depth from Setup (Mobile only)", &IntXXh_List,
    Help 	"When this feature is enabled (Use Interrupt 15h), Video "
    "BIOS will call the interrupt 15h, 5F52h hook, as specified "
    "in the video BIOS reference guide, to get the Panel Color Depth i.e. '18 or 24 BPP'"
    "When disabled, 5F52h will not be called."

    Combo	$H53_Get_EDID_SBIOS, "5F53h - Hook to get EDID from System BIOS:", &IntXXh_List,
    Help	"When this feature is enabled (Use Interrupt 15h), Video "
    "BIOS will call the interrupt 15h, 5F53h hook, as specified "
    "in the video BIOS reference guide, to get the EDID from System BIOS. "
    "When disabled, 5F53h will not be called."

    Combo	$H54_Get_Int_DP_HDMI_Cfg, "5F54h - Hook to get Integrated EFP config from System BIOS:", &IntXXh_List,
    Help	"When this feature is enabled (Use Interrupt 15h), Video "
    "BIOS will call the interrupt 15h, 5F54h hook, as specified "
    "in the video BIOS reference guide, to get the Integrated DP/HDMI configuration from System BIOS. "
    "When disabled, 5F54h will not be called."
  EndPage		; System BIOS Hooks
EndPage		; Legacy VBIOS Configuration

#ENDIF
;============================================================================
; Page - Windows Graphics driver Configuration
;----------------------------------------------------------------------------

Page "Windows Graphics driver Configuration"

  Link "General Features" , "General Features"
  Link "Display Features" , "Display Features"
  Link "Power Conservation" , "Power Conservation"
  Link "Driver Persistence" , "Driver Persistence"

  Page	"General Features"
    Link	"Close Table" , ".."

    EditNum	$VBT_Customization_Version, "  VBT Customization Version:", DEC,
    Help	"This feature allows the OEM to have a customized VBT version "
    "number. The permissible values for VBT Customization version "
    "is from 0 to 255.\r\n"
    
    ;Combo	$Driver_Boot_Device, "  First Boot Display Device:", &OS_Driver_List,
    ;Help	"This feature allows the OEM to select which algorithm to "
    ;"follow on the first boot after the driver has been "
    ;"installed.\r\n"
    ;"\r\n"
    ;"OS Default - If this is selected, the operating system's "
    ;"algorithm will be used.\r\n"
    ;"\r\n"
    ;"Driver Default - If this is selected, the boot device will "
    ;"follow the driver algorithm.  The expected behavior can be "
    ;"found in the Driver PRD chapter:  'First Boot Default "
    ;"Display Resolutions'."

    Combo	$Allow_FDOS_Disp_Switch, "  Allow Full Screen DOS Display Switching:", &No_Yes_List,
    Help	"This feature allows display switching when the system is in "
    "full screen DOS.  When set to yes, display switching will be "
    "allowed while system is in full screen DOS.  When set to no, "
    "display switching will be blocked when system is in full "
    "screen DOS."

    ;    Combo	$Hot_Plug_DVO, "  DVO/SDVO Hot Plug:", &Disabled_Enabled_List,
    ;    Help	"This feature allows the OEM to disable the DVO/SDVO Hot Plug "
    ;    "capability."
    
    Combo	$Enable_LFP_Primary, "  LFP as Primary Display (Mobile only)", &Disabled_Enabled_List,
    Help	"This feature allows the OEM to set the LFP to be the primary "
    "display at all times.  Note:  If this feature is set to "
    "enable, the end-user will not have the capability to set any "
    "other device as primary in the CUI or the OS properties "
    "page. This feature will only affect an LFP connected via the "
    "integrated LVDS."

   ; Combo	$Use_110h_for_LFP, "  Use _DOD 00000110h ID for Primary LFP:", &No_Yes_List,
   ; Help	"This feature when set to yes will use the legacy value "
   ; "00000110h as the ID for primary LFP in the ACPI _DOD, _DGS "
   ; "method.  The ID is passed to the system BIOS through INT10h function 5F64h  "
   ; "The ID 00000110h is the backwards compatible ACPI ID "
   ; "for LFP, which may be necessary in where Microsoft* WindowsXP "
   ; "TabletPC*'s Graphical User Interface is required for Backlight "
   ; "Control(hardcoded by some Windows OSes). In all other cases, "
   ; "the default new ID is strongly preferred."

                    	; Please do not remove the following BMP feature.  It
                    	; is for a special application.

    ;	Combo	$Drv_Int15_hook, "  Enable/Disable VBIOS/Driver INT15 hook:", &Disabled_Enabled_List,
    ;	Help	"This option enables or disables VBIOS/Driver INT15 hook."

    Combo	$DVD_Sprite_Clone, "  Disable Sprite (DVD) in Clone Mode:", &Yes_No_List,
    Help	"This feature when selected 'No', will allow the sprite to be "
    "active during DVD playback when the platform is in a Dual "
    "Display Clone configuration.  Otherwise, when selected 'Yes', "
    "the overlay sprite will be disabled during DVD playback when the "
    "platform is in a Dual Display Clone configuration."

    Combo	$GTF_Mode_Pruning, "  Selective Mode Pruning:", &Disabled_Enabled_List,
    Help	"This feature when enabled will instruct driver software not "
    "to enumerate or set specific display modes determined as "
    "unsupported according to the EDID capabilities of the "
    "display. If the display indicates support for all GTF/DMTS "
    "timings in the display's EDID, then all modes supported by "
    "the graphics host will be enumerated.  If the display does "
    "NOT indicate support for GTF/DMTS timings in the display's "
    "EDID, then some modes/timings that may have been enumerated "
    "by the display driver shall not be set."
    "\r\n"
    "\r\n"
    "Note: This option applies for all display types.  And in the "
    "absence of other platform configuration information (e.g. "
    "OEM Customizable Mode) requiring inclusion of that display "
    "mode/timings."

    ;    Combo	$Sprite_Display_Assign, "  Sprite Display Assignment for When Overlay is Active in Clone Mode:", &Sprite_Display_Lis    t,
    ;    Help	"This feature when set to Primary Display, the driver will "
    ;    "assign the Sprite (2ndary overlay) to the primary display "
    ;    "defined in the current Dual Display Clone configuration, "
    ;    "otherwise when this feature is set to Secondary Display, the "
    ;    "driver will assign the Sprite (2ndary overlay) to the "
    ;    "secondary display defined in the current Dual Display Clone "
    ;    "configuration. Note:  This bit will have no affect if an "
    ;    "application is using the VMR API. "

    ;    Combo	$Enable_Int_Src_Term, "  Enable Internal Source Termination for HDMI:", &Inter_Exter_List,
    ;    Help	"Allows the driver to know to program the HDMI part "
    ;    "to support Internal Source termination mode.\r\n"
    
    Combo	$bmp_Display_Detect, "  Display(s) must be attached for switching Hot Key (Mobile only)", &Yes_No_List,
    Help	"This feature allows a selectable option to determine if "
    "the display device(s) must be attached for BIOS Hot Key display "
    "switches.\r\n"
    "\r\n"
    "If 'No' selected, VBIOS will switch to the next display combination "
    "in toggle list when a display switching hotkey is issued, regardless of"
    "what devices currently attached to the system."
    "\r\n"
    "If 'Yes' selected, VBIOS will switch to the next display combination "
    "only if all the devices in the combination attached to the system.  If "
    "the combination of the attached devices does not match with any device "
    "combination in the toggle list, VBIOS will return failure without any "
    "switching attempt.  The caller should assume that no display change if "
    "failure returned by VBIOS."

    ;Combo	$CUIHotK_Static_Display, "  Display must be attached for CUI/Hot Key (Mobile only)", &Yes_No_List,
    ;Help	"This feature allows a selectable option to determine whether "
    ;"the display device must be attached for CUI Hot Key.\r\n"
    ;"\r\n"
    ;"With the 'No' option the display devices do not have to be "
    ;"attached when enabling the displays via CUI Devices Pages, "
    ;"CUI Hot Key.  Note: This feature may cause the user to have "
    ;"a blank display device due to switching to a display that is "
    ;"not attached.\r\n"
    ;"\r\n"
    ;"With the 'Yes' option the display device must be attached or "
    ;"the display switch attempt will be blocked." 
  EndPage	; General Features"

  Page	"Display Features"
    Link	"Close Table" , ".."

    Combo	$CUI_Maintain_Aspect, "  Enable 'Maintain Aspect Ratio':", &No_Yes_List,
    Help	"This feature allows the OEM to enable or disable the 'Maintain "
    "Aspect Ratio' feature.  When the option is set to Yes, the "
    "feature will be enabled and CUI will show for end user "
    "selection 'Maintain Aspect Ratio'.  When the option is set to "
    "No, the complete 'Maintain Aspect Ratio' feature will be disabled."

    ; Combo	$Preserve_Aspect_Ratio, "  Preserve Aspect Ratio:", &Disabled_Enabled_List,
    ; Help	"This feature allows the OEM to configure the default option "
    ; "for aspect ratio settings. When enabled, the CUI will reflect "
    ; "preserve the aspect ratio as active setting.  Otherwise, when "
    ; "disabled, the CUI will use the setting 'Panel Fitting Initial "
    ; "States' as default aspect ratio setting.  This option will "
    ; "only be available for initial boot value. Any subsequent "
    ; "change in CUI will have higher priority."

    Title      "    "
    Title      "Legacy Monitor Mode Limit"
    EditNum	$Legacy_Monitor_Max_X, "  Maximum X Resolution (Pixels):", DEC,
    Help	"This feature allows the limiting of selectable display modes "
    "when a legacy monitor is detected.  The maximum resolution is "
    "specified by a maximum number of horizontal active pixels."
    "\r\n"
    "Note: A legacy monitor is defined as a monitor with no DDC "
    "available."

    EditNum	$Legacy_Monitor_Max_Y, "  Maximum Y Resolution (Pixels):", DEC,
    Help	"This feature allows the limiting of selectable display modes "
    "when a legacy monitor is detected.  The maximum resolution is "
    "specified by a maximum number of vertical active pixels."
    "\r\n"
    "Note: A legacy monitor is defined as a monitor with no DDC "
    "available."

    EditNum	$Legacy_Monitor_Max_RR, "  Maximum Refresh Rate (Hz):", DEC,
    Help	"This feature allows the limiting of selectable display modes "
    "when a legacy monitor is detected.  The maximum refresh rate "
    "is specified in Hz."
    "\r\n"
    "Note: A legacy monitor is defined as a monitor with no DDC "
    "available."

    Title      "    "
    Title      "Rotation Configuration"

    Combo	$Rot_Enable, "  Enable Rotation:", &No_Yes_List,
    Help	"This feature when set to yes, will allow for rotation.  "
    "Otherwise, when the feature is set to no, the rotation "
    "functionality will be disabled within the driver."

    Title      "    "
    Title      "Graphics Mode to Boot on Windows"

    EditNum	$Driver_Boot_Mode_X, "  X Resolution (Pixels):", DEC,
    Help	"This feature allows the OEM to select which resolution the "
    "system will use on the first reboot after the driver has "
    "been installed.\r\n"
    "\r\n"
    "X Resolution (Pixels)\r\n"
    "\r\n"
    "Note: This feature is only used when the Boot Display "
    "Algorithm is set to Driver Default."

    EditNum	$Driver_Boot_Mode_Y, "  Y Resolution (Pixels):", DEC,
    Help	"This feature allows the OEM to select which resolution the "
    "system will use on the first reboot after the driver has "
    "been installed.\r\n"
    "\r\n"
    "Y Resolution (Pixels)\r\n"
    "\r\n"
    "Note: This feature is only used when the Boot Display "
    "Algorithm is set to Driver Default."

    EditNum	$Driver_Boot_Mode_BPP, "  Color Depth (Bits/Pixel):", DEC,
    Help	"This feature allows the OEM to select which resolution the "
    "system will use on the first reboot after the driver has "
    "been installed.\r\n"
    "\r\n"
    "Color Depth (BPP)\r\n"
    "\r\n"
    "Note: This feature is only used when the Boot Display "
    "Algorithm is set to Driver Default."

    EditNum	$Driver_Boot_Mode_RR, "  Refresh Rate (Hz):", DEC,
    Help	"This feature allows the OEM to select which resolution the "
    "system will use on the first reboot after the driver has "
    "been installed.\r\n"
    "\r\n"
    "Refresh Rate (Hz)\r\n"
    "\r\n"
    "Note: This feature is only used when the Boot Display "
    "Algorithm is set to Driver Default."

    Title      "     "
    Title      "TV features"

    Combo	$Under_Over_Scan_Via_YPrPb, "  Enable underscanned modes for HDTV via Component (YPrPb):", &Under_Over_List,
    Help	"For 720p format when enable underscan and overscan modes "
    "option is selected, expose 1184x666 and 1280x720 through CUI"
    "\r\n"
    "For 1080i format when enable underscan and overscan modes "
    "option is selected, expose 1776x1080 and 1920x1080 through CUI"

    Combo	$Under_Over_Scan_Via_DVI, "  Enable underscanned modes for HDTV via HDMI:", &Under_Over_List,
    Help	"When 720p is found in the EDID structure of the active HDMI "
    "display and enable underscan modes is selected, 1184x666 will "
    "be available and be centered in 720p timings when enabled. "
    "\r\n"
    "When 1080i or 1080p is found in the EDID structure of the "
    "active DVI display and enable underscan modes is selected, "
    "1776x1000 will be centered in appropriate 1080 timings. "

    Title	"\r\n"
    Title	"  Add 1776x1000 when 1080i is selected and add 1184x666 when 720p is selected for HDTV via HDMI:"
    Combo	$Add_Overscan_Mode, " ", &Disabled_Enabled_List,
    Help	"For 1080i format, 1776x1000 will be made available in CUI "
    "along with native resolution 1920x1080.  For 720p format, "
    "1184x666 will be made available in CUI along with native "
    "resolution 1280x720. These resolutions are exposed to get the "
    "HDMI image under scanned with task bar visible."
  EndPage	; Display features

  Page	"Power Conservation"
    Link	"Close Table" , ".."

    Combo	$SDVO_Device_Power_Down, "  SDVO device Power down:", &Disabled_Enabled_List,
    Help	"This feature Powers down the SDVO device when the system is "
    "running in battery mode (DC) and the corresponding display "
    "not connected."

    Title	"	"

    Combo	$PC_Fields_Enable, "  PC Features Control Options", &Disabled_Enabled_List,
    Help	"This feature determines the validity of the following PC Features Control Options.\r\n\r\n"
    "1.  Intel® Rapid Memory Power Management (RMPM)\r\n"
    "2.  Intel® Smart 2D Display Technology (S2DDT)\r\n"
    "3.  Intel® Display Power Saving Technology (DPST) (Mobile only)\r\n"
    "4.  DxgkDDI Backlight Control (DxgkDdiBLC) (Mobile only)\r\n"
    "5.  Intel® Automatic Display Brightness (ADB) (Mobile only)\r\n"
    "6.  Intel® Display Refresh Rate Switching (DRRS) (Mobile only)\r\n"
    "7.  Graphics Render Standby (RS)\r\n"
    "8.  Graphics Power Modulation Technology (GPMT) (Mobile only)\r\n"
    "9.  Intel Turbo Boost Technology\r\n"
    "10. Dynamic Frames Per Second (DFPS)\r\n"
	"11. Dynamic Media Refresh Rate Switching (DMRRS)\r\n"
	"12. Assertive Display Technology (ADT)\r\n\r\n"
    "Note: Enable and Save the changes to display all the PC Features Control Options\r\n"

    Combo	$PM_RMPM_Enable, "      Intel® Rapid Memory Power Management (RMPM)", &Disabled_Enabled_List,
    Help	"This feature determines whether Intel® Rapid Memory Power Management (RMPM) is to be "
    "enabled. "

    Combo	$PM_S2DDT_Enable, "      Intel® Smart 2D Display Technology (S2DDT)", &Disabled_Enabled_List,
    Help	"This feature determines whether Intel® Smart 2D Display Technology (S2DDT) is to be "
    "enabled. "

    Combo	$PM_DPST_Enable, "      Intel® Display Power Saving Technology (DPST) (Mobile only)", &Disabled_Enabled_List,
    Help	"This feature determines whether the Intel® Display Power "
    "Savings Technology (DPST) is enabled or disabled.  Intel® DPST "
    "is a display Power savings technology that changes the "
    "intensity of colors in order to conserve backlight Power."
    "\r\n\r\nNote: This technology is only active when the system "
    "is running in battery mode and the LFP is the only active "
    "display device."
    
    Combo	$BIA_Aggress_Level, "          DPST Aggressiveness Level (Mobile only)", &Pwr_Pref_List,
    Help	"This feature defines the Intel® Display Power Saving Technology "
    "aggressiveness level if and only if the feature Intel® Display Power Saving "
    "Technology is enabled."   
    "\r\n\r\nThe following are the definitions for each level:"
    "\r\n1 - Maximum Quality - shall use no DPST "
    "\r\n2 - Provides  the user the maximum "
    "brightness for their embedded Local Flat Panel (LFP)while DPST is in use"
    "\r\n3 - This level defines maximum amount of brightness with "
    "minimal Power savings"
    "\r\n4 - This level defines an intermediate value for brightness amount"
    "\r\n5 - This level defines an intermediate value for the brightness amount"
    "\r\n6 - Maximum Battery - Provided the user with the minimum amount of "
    "brightness capable for their LFP with the maximum Power savings"

    Combo	$PM_BLC_Enable, "      DxgkDDI Brightness Control Method (Mobile only)", &Disabled_Enabled_List,
    Help	"This option determines whether the Vista, Win7, and future version DxgkDDI LFP Brightness Control method is to be enabled. "

    Combo	$PM_ADB_Enable, "      Intel® Automatic Display Brightness (ADB) (Mobile only)", &Disabled_Enabled_List,
    Help	"This feature determines whether Intel® Automatic Display Brightness is to be "
    "enabled.  Intel® Automatic Display Brightness adjusts the brightness of the "
    "embedded Local Flat Panel (LFP) depending on the current "
    "ambient light environment.  When enabled, the driver and VBIOS"
    " will control the backlight brightness of the LFP depending "
    "on the ambient environment if and only if the LFP is the only "
    "active display.  When disabled, the driver and VBIOS will "
    "perform no action."

    Link "ADB Response Data (Mobile only)" , "ADB Response Data (Mobile only)"

    Combo	$PM_DRRS_Enable, "      Intel® Display Refresh Rate Switching (DRRS) (Mobile only)", &Disabled_Enabled_List,
    Help	"This feature determines whether Intel® Display Refresh Rate Switching (DRRS) is to be "
    "enabled. "

    Combo	$PM_RS_Enable, "      Graphics Render Standby (RS)", &Disabled_Enabled_List,
    Help	"This feature determines whether Graphics Render Standby (RS)is to be enabled. "

    Combo	$PM_GPMT_Enable, "      Graphics Power Modulation Technology (GPMT) (Mobile only)", &Disabled_Enabled_List,
    Help	"This feature determines whether Graphics Power Modulation Technology (GPMT) is to be "
    "enabled. " 		
    
    Combo	$PM_Turbo_Enable, "      Intel® Turbo Boost Technology", &Disabled_Enabled_List,
    Help	"This feature determines whether Intel Turbo Boost Technology is to be enabled. "
    
      Combo	$Panel_Self_Refresh, "      Panel Self Refresh (PSR)", &Disabled_Enabled_List,
      Help	"This feature determines whether Panel Self Refresh (PSR) feature is to be enabled. "

        Combo	$Inter_Pixel_Storage, "      Intel® Intermediate Pixel Storage (IPS) Technology", &Disabled_Enabled_List,
        Help	"This feature determines whether Intermediate Pixel Storage (IPS) Technology is to be enabled. "

	Combo	$Dynamic_FPS_Enable, "      Dynamic Frames Per Second (DFPS)", &Disabled_Enabled_List,
    Help	"This feature determines whether Dynamic Frames Per Second is to be enabled. "
	
	Combo	$DMRRS, "      Dynamic Media Refresh Rate Switching Enable/Disable", &Disabled_Enabled_List,
	Help	"This feature determines whether Dynamic media refresh rate switching is to be enabled. "
	
	Combo	$ADT, "      Assertive Display Technology Enable/Disable", &Disabled_Enabled_List,
	Help	"This feature determines whether Assertive display technology is to be enabled. "
    
    Page	"ADB Response Data (Mobile only)"
      Link	"Close Table" , ".."

      Table	$ALS_Response_Data " ADB Response Data (Mobile only)",
      Column	"Backlight Adjust", 2 bytes, EHEX
      Column	"Lux", 2 bytes, EHEX,
      Help	"This feature defines values used to calibrate the "
      "Intel® Automatic Display Brightness policy's "
      "response to account for specific hardware implementation "
      "details such as sensor placement and optics.  Up to five "
      "points can be specified, where each point indicates a given "
      "ambient light illuminance to display luminance mapping "
      "specified as (<%BacklightAdjust>, <Lux>).  Points should be "
      "listed in monotonically increasing order by ambient light "
      "illuminance (lux).  A minimum of two points are required "
      "(min and max)."
    EndPage	; "ADB Response Data"
  EndPage		; Power Conservation
  
  Page	"Driver Persistence (Mobile only)"
    Link	"Close Table" , ".."

    Combo	$Driver_Persist_PM, "  Mode Persistence on a Power Management Event:", &OS_DriverP_List,
    Help	"This feature allows mode persistence to be enabled on a "
    "Power management event.\r\n"
    "\r\n"
    "If mode persistence is disabled, the OS Default Algorithm "
    "will be applied.\r\n"
    "\r\n"
    "If mode persistence is enabled, the Driver Algorithm will be "
    "used and the appropriate Display Configuration will be "
    "applied for the current State.\r\n"
    "\r\n"
    "Note: State refers to the attached devices (or lack of "
    "devices) as well as the display configuration (resolution, "
    "refresh rate and color depth for each device as well as the "
    "multi-display configuration information)."
    
    Combo	$Driver_Persist_Lid_Switch, "  Mode Persistence on a  Lid Switch event:", &OS_DriverP_List,
    Help	"This feature allows mode persistence to be enabled on a "
    "Lid Switch event.\r\n"
    "\r\n"
    "If mode persistence is disabled, the OS Default Algorithm "
    "will be applied.\r\n"
    "\r\n"
    "If mode persistence is enabled, the Driver Algorithm will be "
    "used and the appropriate Display Configuration will be "
    "applied for the current State.\r\n"
    "\r\n"
    "Note: State refers to the attached devices (or lack of "
    "devices) as well as the display configuration (resolution, "
    "refresh rate and color depth for each device as well as the "
    "multi-display configuration information)."

    Combo	$Driver_Persist_Hotkey, "  Mode Persistence on a  Hot Key Event:", &OS_DriverP_List,
    Help	"This feature allows mode persistence to be enabled on a Hot "
    "Key event.\r\n"
    "\r\n"
    "If mode persistence is disabled, the OS Default Algorithm "
    "will be applied.\r\n"
    "\r\n"
    "If mode persistence is enabled, the Driver Algorithm will "
    "be used and the appropriate Display Configuration will be "
    "applied for the current State.\r\n"
    "\r\n"
    "Note:  State refers to the attached devices (or lack of "
    "devices) as well as the display configuration (resolution, "
    "refresh rate and color depth for each device as well as the "
    "multi-display configuration information)."

    Combo	$Driver_Persist_Docking, "  Mode Persistence on a Dock/Undock event:", &OS_DriverP_List,
    Help	"This feature allows mode persistence to be enabled on a "
    "Dock/Undock event.\r\n"
    "\r\n"
    "If mode persistence is disabled, the OS Default Algorithm "
    "will be applied.\r\n"
    "\r\n"
    "If mode persistence is enabled, the Driver Algorithm will "
    "be used and the appropriate Display Configuration will be "
    "applied for the current State.\r\n"
    "\r\n"
    "Note: State refers to the attached devices (or lack of "
    "devices) as well as the display configuration (resolution, "
    "refresh rate and color depth for each device as well as the "
    "multi-display configuration information).\r\n"

    Combo	$PersistHotkeyRestoreCloneMDS, "  On Hot-Key Event enable MDS/ Dual Display Clone:", &No_Yes_List,
    Help	"This feature allows the OEM to determine if the system "
    "should go into extended desktop on a Hot-Key persistence "
    "event.\r\n"
    "\r\n"
    "If No, extended desktop will be saved/applied.\r\n"
    "\r\n"
    "If Yes, extended desktop will not be saved/applied.  "
    "Instead, Dual Display Clone will be utilized.\r\n"
    "\r\n"
    "This feature can only be used if the OEM has enabled mode "
    "persistence on a hot-key event."

    Combo	$PersistHotkeyRestoreRefreshrate, "  On Hot Key Event, Save Refresh Rate:", &No_Yes_List,
    Help	"This feature allows the OEM to determine if the Refresh Rate "
    "should be saved/applied on a hot-key event.\r\n"
    "\r\n"
    "This feature can only be used if mode persistence has been "
    "enabled on a hot-key event."

    Combo	$PersistHotkeyRestorePipe, "  On Hot Key Event, Save Pipe Configuration Information:", &No_Yes_List,
    Help	"This feature allows the OEM to determine if the Pipe "
    "Configuration information should be saved/applied on a "
    "hot-key event.\r\n"
    "\r\n"
    "This feature can only be used if mode persistence has been "
    "enabled on a hot-key event."

    Combo	$PersistHotkeyRestoreMode, "  For Hot Key Persistence on Restore Mode:", &No_Yes_List,
    Help	"This feature allows the OEM to determine if the Mode "
    "information should be saved/applied on a hot-key event.\r\n"
    "\r\n"
    "This feature can only be used if mode persistence has been "
    "enabled on a hot-key event."

    Combo	$PersistEDIDRestoreMode, "  Enable EDID Persistence for Restore Mode:", &No_Yes_List,
    Help	"This option allows the OEM to utilize information from the "
    "EDID of a device when a mode persistence event occurs.\r\n"
    "\r\n"
    "Note: This feature can only be used if mode persistence has "
    "been enabled on hotkey / lid switch / Power persistence."

    Combo	$PersistHotPlugRestoreMode, "  Hot Plug Persistence on Restore Mode:", &No_Yes_List,
    Help	"This feature allows mode persistence to be enabled when a "
    "any display device is Hot-Plugged into the system.\r\n"
    "\r\n"
    "If NO is selected, the device will still appear in the "
    "properties pages (OS and CUI), but the current display "
    "configuration will not change.\r\n"
    "\r\n"
    "If YES is selected, hot-plug persistence will restore the "
    "last known state prior to the disconnection of the display "
    "device."
    
    EditNum	$PersistMaxConfig, "  Maximum # of Persistence States:", DEC,
    Help	"This feature allows the OEM to determine the number of "
    "configuration States to be saved by the registry.  The "
    "selectable range is from 10-200.\r\n"
    "\r\n"
    "Note: This feature can only be used when 'Enable EDID "
    "persistence for Restore Mode' is selected."
  EndPage	; "Driver Persistence"
EndPage		; "Windows Graphics driver Configuration"	

;==============================================================================
; Page - Display Configurations
;------------------------------------------------------------------------------
Page  "Integrated Display configuration"
  Title	"Integrated CRT, DP, HDMI, DVI, eDP configuration"
  
  Link  "Integrated CRT configuration", "Integrated CRT configuration"
  Link  "Integrated DisplayPort/HDMI Configuration with External Connectors", "Integrated DisplayPort/HDMI Configuration with External Connectors"
  Link  "LFP Configuration", "LFP Configuration"

  ;==============================================================================
  ; Page - Integrated CRT configuration
  ;------------------------------------------------------------------------------

  Page "Integrated CRT configuration"
    Title	"Integrated CRT configuration"

    Link	"Close Window" , ".."

    Combo	$Int_CRT_Support, "  Integrated CRT Support:", &Disabled_Enabled_List,
    Help	"This feature when set to 'Enabled' allows to enable CRT functionality in software.\n "
    "Note: To enable 4 lane eDP panel on Haswell and Broadwell, Integrated CRT Support has to be disabled."

    Combo	$CRT_DDC_GMBUS_Pin, "  Analogue CRT DDC GPIO pin pair:", &GPIO_Pin_List,
    Help	"This feature allows users to select I2C pin pair to access Analogue DDC. \r\n"
    "Intel suggests following default Pin Pair map.  OEMs should select "
    "appropriate Pin Pair if they remap these functions onto other pins.\r\n"
    "\r\n"
    "\r\n"
    "GMBUS Port#	Functions\r\n"
    "1	               I2C GPIO pins \n"
    "2	               Analog CRT DDC GPIO pins \n"
    "5	               Integrated HDMI-B DDC GPIO Pins \n"
    "4	               Integrated HDMI-C DDC GPIO Pins \n"
    "6	               Integrated HDMI-D DDC GPIO Pins \n"
    Combo	$Hot_Plug_CRT, "  CRT Hot Plug:", &Disabled_Enabled_List,
    Help	"This feature allows the OEM to disable the CRT Hot Plug "
    "capability. This is applicalbe only for driver hotplug in driver environment and not DOS (VBIOS mode)"

    Combo	$Single_DVI_I, "  Single DVI-I connector for CRT and DVI display: ", &No_Yes_List,
    Help	"This option allows single DVI-I connector to support CRT or "
    "DVI display devices using EDID byte 14 bit 7 to distinguish "
    "between them."  
  EndPage           ; Integrated CRT configuration

  ;==============================================================================
  ; Page - LVDS Configuration
  ;----------------------------------------------------------------------------

  Page	"LFP Configuration"
    Link	"Close Table", ".."
    Combo	$LVDS_Config , "Active Local Flat Panel Configuration", &LVDS_Config_List,
    Help	"This feature allows to configure LFP display. \n"
    "Note: To enable 4 lane eDP panel on Haswell and Broadwell, Integrated CRT Support has to be disabled.\n"
    "Note: For desktop platforms, eDP supported only on Port D"

    Title "    "      
    Combo	$Int_eDP_Port, "Select Output port (Port-A for Mobile only)", &eDP_Port_List,
    Help	"This feature, when enabled, will activate support for an eDP "
    "to be configurable on Port A or Port D. "
    "Driver also uses the same data for enabling eDP on the selected port "
    "\r\n Note: Do not enable any other digital ports on the same Port as eDP"

    Combo	$Int_LFP_AUX_Channel, "Select AUX Channel (AUX Channel-A for Mobile only)", &Int_eDP_AUX_Channel_List,
    Help	"This feature specifies the AUX Channel for embedded-DisplayPort. "
    "This field is valid only if integrated eDP is selected for Device Type."

    ;  #IF	$Integrated_LVDS == 1	; $Integrated_LVDS == TRUE
    ;    Combo	$LFP_DDC_GMBUS_Pin, "  LFP DDC GPIO pin pair:", &GPIO_Pin_List,
    ;    Help	"This feature allows users to select I2C pin pair to access Integrated LVDS DDC. \r\n"
    ;    "Following is default Pin Pair map suggested by Intel.  OEMs should select "
    ;    "appropriate Pin Pair if they remap these functions onto other pins.\r\n"
    ;    "\r\n"
    ;    "\r\n"
    ;    "GMBUS Port#	Functions\r\n"
    ;    "  0		Analogue CRT DDC\r\n"
    ;    "  1		SSC clock access\r\n"
    ;    "  2		Integrated LVDS DCC\r\n"
    ;    "  4		SDVO Registers/DDC/SPD\r\n"
    ;  #ENDIF	; $Integrated_LVDS == TRUE

    Title "    "
    Combo	$bmp_Panel_type, "Select Panel Type:", &Panel_List, 
    Help	"This feature selects the Local Flat Panel (LFP) the VBIOS "
    "and driver is to enable.\r\n" 
    "\r\n"
    "Note, a valid return from the system BIOS hook 5F40h will "
    "replace this default value.\r\n"
    "\r\n"
    "Default LFP parameter values:\r\n"
    "\tPANEL #01: 640x480 LFP\r\n"
    "\tPANEL #02: 800x600 LFP\r\n"
    "\tPANEL #03: 1024x768 LFP\r\n"
    "\tPANEL #04: 1280x1024 LFP\r\n "
    "\tPANEL #05: 1400x1050 Reduced Blanking LFP\r\n"
    "\tPANEL #06: 1400x1050 Non-Reduced Blanking LFP\r\n"
    "\tPANEL #07: 1600x1200 LFP\r\n"
    "\tPANEL #08: 1280x768 LFP\r\n"
    "\tPANEL #09: 1680x1050 LFP\r\n"
    "\tPANEL #10: 1920x1200 LFP\r\n"
    "\tPANEL #11: 1440x900 LFP\r\n"
    "\tPANEL #12: 1600x900 LFP\r\n "
    "\tPANEL #13: 1024x768 LFP\r\n"
    "\tPANEL #14: 1280x800 LFP\r\n"
    "\tPANEL #15: 1920x6108 LFP\r\n"                                
    "\tPANEL #16: 2048x1536"                                

    Combo	$bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", &Disabled_Enabled_List,
    Help	"This feature, when enabled, will activate support for a LFP "
    "with an EDID.  The video BIOS and drivers will load the EDID "
    "and use its data to set appropriate timing on current panel.  "
    "If disabled, there will be no attempt to read an EDID and other methods "
    "will be used to set panel timing."
   ; "\r\n\r\nNote:  The backlight data may need to be updated." 
   ; "\r\n       The <LFP DDC GPIO pin pair> option on page General"
   ; " Features must be correct for platform."


    Combo	$LFP_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
    Help	"This feature, when enabled, will set lane reversal bit for Selected Port "
   
   
    Title "    "

    Link "Panel #1 ", "Panel #1 "
    Link "Panel #2 ", "Panel #2 "
    Link "Panel #3 ", "Panel #3 "
    Link "Panel #4 ", "Panel #4 "
    Link "Panel #5 ", "Panel #5 "
    Link "Panel #6 ", "Panel #6 "
    Link "Panel #7 ", "Panel #7 "
    Link "Panel #8 ", "Panel #8 "
    Link "Panel #9 ", "Panel #9 "
    Link "Panel #10 ", "Panel #10 "
    Link "Panel #11 ", "Panel #11 "
    Link "Panel #12 ", "Panel #12 "
    Link "Panel #13 ", "Panel #13 "
    Link "Panel #14 ", "Panel #14 "
    Link "Panel #15 ", "Panel #15 "
    Link "Panel #16 ", "Panel #16 "

    ;==============================================================================
    ; Page - Panel #1 (640x480 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------

    Page "Panel #1 "

      Title	"Local Flat Panel (LFP) Size"

      
      EditText   $Panel_Name_01, "LFP panel name:", 
      Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "
      

      EditNum	$Panel_Width_01, "LFP Width:", DEC,
      Help	"This value specifies the LFP pixel width for this panel "
      "type."

      EditNum	$Panel_Height_01, "LFP Height:", DEC,
      Help	"This value specifies the LFP pixel height (number of scan "
      "lines) for this panel type."
      
     Combo    $eDP_VSwingPreEmph_1, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
      Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
    "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

 
      Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      
      Link "DTD Timings Table" , "DTD Timings"
      Link "LFP PnP ID Table" , "LFP PnP ID"
      Link "Backlight Control Parameters" , "Backlight Control Parameters"
      Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	  	    Link "Chromaticity Control" , "Chromaticity Control"

      #IF	0; $LVDS_Config == 3; Int eDP
        Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
      #ENDIF	; eDP

        ;        #IF	$LVDS_Config == 1 ; Int LVDS
        ;          Combo	$Int_LVDS_Panel_1_Channel_Type, "Integrated LVDS Channel Type:", &INT_LVDS_Channel_List,
        ;          Help	"SETTINGS :\r\n"
        ;          "Single Channel : this option will initialize the Integrated LVDS Port Control for Single Channel.\r\n"
        ;          "Dual Channel : this option will initialize the Integrated LVDS Port Control for Dual Channel.\r\n"
        ;          "Automatic Selection : this option will implement the following algorithm for initializing the Integrated LVDS Port         Control with respect to Channel Selection.\r\n"
        ;          "Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
        ;          "			   X >= 1280, Check Y-Resolution.\r\n"
        ;          "Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
        ;          "			  Y > 800, Set LVDS for Dual Channel.\r\n"
        ;        #ENDIF	; $LVDS_Config == 1 ; Int LVDS

        ;        #IF	$LVDS_Config == 1 
        ;          Combo	$INT_Panel_Color_Depth01, "Panel Color Depth:", &Panel_Color_Depth_List,
        ;          Help	"This feature specifies the color depth of the integrated LVDS panel used. "
        ;        #ENDIF	; $LVDS_Config == 1 

      #IF	$LVDS_Config == 3 ; eDP
        Combo	$eDP_Panel_Color_Depth_01, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
        Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      

      #IF	$LVDS_Config == 1 ; Int LVDS
        Title	"Spread Spectrum Clock Features"
        Combo	$Enable_SSC01, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
        Help	"This feature when enabled will instruct software to use the "
        "external Spread Spectrum input clock as the internal LFP "
        "PLL reference clock.  Otherwise, when disabled, the internal "
        "reference clock will be used as the internal LFP PLL "
        "reference clock ignoring any Spread Spectrum input clock.\r\n"
        "\r\n"
        "Note: When enabling SSC option, please make sure that the hardware/"
        "system BIOS has enabled this feature in the chipset platform. "
        "The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
        "option must match the actual SSC frequency determined by platform "
        "hardware and/or system BIOS."
        "\r\n"
        "Note: This option is for internal LFP only.\r\n"
        "\r\n"
        "Note: Currently, this feature will also replace the CRT PLL "
        "reference clock on the same pipe that may cause CRT jitter.  "
        "Ideas to help this situation are to remove single pipe "
        "simultaneous display combinations (dual display twin) or use "
        "the 'Disable SSC in Dual Display Twin' option to "
        "automatically switch back to internal reference clock when "
        "entering a dual display twin display combination."
        Combo	$SSC_Freq01, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
        Help	"The SSC frequency selected must match the actual SSC frequency "
        "determined by platform hardware and/or system BIOS.\r\n"
        Combo	$Disable_SSC_DDT01, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
        Help	"This feature allows a selectable option for OEMs to disable "
        "Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
        "Pipe Simultaneous mode.\r\n"
        "\r\n"
        "Note: Disabling means that SSC will not be enabled while "
        "Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
        "when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP

        Title	"eDP Spread Spectrum Clock Features"
        Combo	$Enable_SSC01, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
        Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
      
	  #ENDIF	; $LVDS_Config == 1 ; Int LVDS


      #IF	$LVDS_Config == 3 ; eDP
        Combo	$edp_S3D_Feature_01, "  Steroscopic 3D:", &Disabled_Enabled_List,
        Help	"This feature allows a selectable option to determine whether "
        "to enable/disable S3D feature in driver.\r\n"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      Title	"DPS Panel Type Features (Mobile only)"
      Combo	$DPS_Panel_Type_01, "  DPS Panel Type:", &DPS_Panel_Type_List,
      Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
      "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
      "which reduces display Power\r\n"
      "SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
      "rate will not adversely impact the user experience\r\n"
      "Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
      "rate will not adversely impact the user experience.Implements seamless refresh\r\n"
      "rate switching, which eliminates the screen blink that occurred\r\n" 
      "during the refresh rate transitions\r\n"
      

      #IF	$Chipset >= 17 && $Chipset <= 18	; SNB

        #IF	$LVDS_Config == 3 ; eDP
          Combo	$eDP_sDRRS_MSA_Delay_01, "  MSA Timing Delay:", &MSA_TimingDelay_List,
          Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
          "The sDRRS timing switch shall occur on same line as the MSA\r\n"
          "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
          "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
          "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
          "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
        #ENDIF	; $LVDS_Config == 3 ; eDP

      #ENDIF	; SNB

      Title	"BackLight Technology Type Features (Mobile only)"
      Combo	$Blt_Control_01, "  BackLight Technology:", &Blt_Control_Type_List,
      Help     "This feature allows OEM to select the Backlight Technology.\r\n "
      
      #IF	$Chipset >= 19		; IVB and above 
	     #IF  $LVDS_Config == 3	; Int eDP
		   Title " "
                   Link "PSR feature" ,"PSR feature"
	     #ENDIF			; eDP
     #ENDIF				; IVB and above

      #IF	$LVDS_Config == 1 ; Int LVDS
        Page "Panel Power Sequencing"
          
          Link	"Close Table" , ".."
          
          EditNum	$Power_On_Backlight_Enable_Delay_01, "  Power On to Backlight Enable Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for delay of Power on to backlight enable."

          EditNum	$PowerUpDelay_01, "  Panel Power Up Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for panel Power up delay. Note: This value "
          "is typically T1 + T2."

          EditNum	$Power_Backlight_Off_Power_Down_Delay_01, "  Power Backlight Off to Power Down Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for Power backlight off to Power down delay."

          EditNum	$PowerDownDelay_01, "  Panel Power Down Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for Power down delay."
          
          EditNum	$PowerCycleDelay_01, "  Panel Power Cycle Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for Power Cycle delay."
          "\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
          "to have a delay of 400ms, programming value should be 5 instead of 4"
          
        EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
        Page	"Panel Power Sequencing"
          Link	"Close Table", ".."
		 
			Combo	$eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"
          
			EditNum    $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"

      EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS

      

      Page "DTD Timings"
        
        Link	"Close Table" , ".."

        Table	$DVO_Tbl_01 " DTD Timings Values",
        Column "Timings" , 1 byte , EHEX,
        Help	"This feature allows for the definition of the DTD "
        "timings parameters related to the LFP.  The "
        "table is the 18-byte DTD structure defined in the "
        "VESA EDID version 1.x.\r\n"  
        "\r\n"
        "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
        "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
        "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
        "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
        "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
        "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
        "\tByte6 \t: Vertical Active in lines, LSB\r\n"
        "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
        "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
        "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
        "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
        "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
        "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
        "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
        "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
        "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
        "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
        "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
        "\tByte13 \t: Horizontal Image Size, LSB\r\n"
        "\tByte14 \t: Vertical Image Size, LSB\r\n"
        "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
        "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
        "\tByte16 \t: Horizontal Border in pixels\r\n"
        "\tByte17 \t: Vertical Border in lines\r\n"
        "\tByte18 \t: Flags:\r\n"
        "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
        "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
        "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
        "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
        "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
        "\t   \t:   Bit 0:   0 = Reserved"
      EndPage

      Page "LFP PnP ID"

        Link	"Close Table" , ".."

        Table	$LVDS_PnP_ID_01 " LFP PnP ID Values",
        Column "PnP ID" , 1 byte , EHEX,
        Help	"This feature allows the 10 bytes of EDID Vendor / "
        "Product ID starting at offset 08h to be used as a "
        "PnP ID.\r\n"
        "\r\n"
        " Table Definition:\r\n"
        "  Word:  ID Manufacturer Name\r\n"
        "  Word:  ID Product Code\r\n"
        "  DWord: ID Serial Number\r\n"
        "  Byte:  Week of Manufacture\r\n"
        "  Byte:  Year of Manufacture"
      EndPage

      Page "Backlight Control Parameters"

        Link	"Close Table" , ".."

        Combo	$BLC_Inv_Type_1, "  Inverter Type:", &Inv_Type_List,
        Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

        Combo	$BLC_Inv_Polarity_1, "  Inverter Polarity:", &Inv_Polarity_List,
        Help	"This feature allows the backlight inverter polarity "
        "to be specified.\r\n"
        "\r\n"
        "Normal means 0 value is minimum brightness.\r\n"
        "Inverted means 0 value is maximum brightness."

        EditNum	$BLC_Min_Brightness_1, "  Minimum Brightness:", DEC,
        Help	"This feature allows defining the absolute minimum "
        "backlight brightness setting.  The graphics driver "
        "will never decrease the backlight less than this "
        "value.  The value must be specified using normal "
        "polarity semantics."

        EditNum	$POST_BL_Brightness_01, "  POST Brightness:", DEC,
        Help	"This feature is used only by video BIOS to set initial "
        "brightness level at POST. \r\n"
        "This is configurable field of 0-255. "
        "Value of 0 inidicates Zero brightness, 255 indicates maximum "
        "brightness."

        EditNum	$PWM_Frequency_1, "  PWM Inverter Frequency (Hz):", DEC,
        Help	"This feature allows for the definition of the "
        "frequency needed for PWM Inverter.\r\n"
        "\r\n"
        "Note: The frequency range, entered as a decimal "
        "number, for the integrated PWM is 200Hz - 40KHz."

                  ;          Combo	$BLC_GPIO_Pins_1, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
                  ;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
                  ;          "this device."

                  ;          Combo	$BLC_GMBus_Speed_1, "  I2C Bus Frequency:", &GMBus_Speed_List,
                  ;          Help	"Selects the I2C bus frequency to use when "
                  ;          "communicating to this device."

                  ;          EditNum	$BLC_I2C_Addr_1, "  I2C Device Address:", HEX,
                  ;          Help	"Selects the I2C device address for communication to "
                  ;          "this backlight inverter.  The device address should "
                  ;          "be in 8-bit format with the slave address assigned to "
                  ;          "bits 7:1 and bit 0 cleared.  For example, the slave "
                  ;          "address 0101100b would be stated here as 58h."

                  ;          EditNum	$BLC_Brightness_Cmd_1, "  I2C Device, Display Brightness Command Code:", HEX,
                  ;          Help	"Selects the command code (register index) for setting "
                  ;          "the backlight brightness."
      EndPage
	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_1, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_1, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_1, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0"
	    	EditNum	$Blue_White_1, "   Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_1, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_1, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_1, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_1, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_1, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_1, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_1, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_1, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

      #IF	$LVDS_Config == 3 ; eDP
        Page "eDP Fast Link Training Configuration Parameters"

          Link	"Close Table" , ".."
          
          Combo	$Fast_Link_Training_Supported_01, "  Is FastLinkTraining Feature Supported:", &No_Yes_List,
          Help	"This feature allows for the selection of the "
          "Fast Link Training feature is to be enabled or disabled."
          
          Combo	$eDP_Link_DataRate_01, "  Data Rate:", &eDP_Link_DataRate_List,
          Help	"This feature allows for the selection of the "
          "Data Rate for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training."

          Combo	$eDP_Link_LaneCount_01, "  Lane Count:", &eDP_Link_LaneCount_List,
          Help	"This feature allows for the selection of the "
          "Lane Count (Port Width) for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training."

          Combo	$eDP_Link_PreEmp_01, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
           Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training.\n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
	      "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_01, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
         
    EndPage
      
	 #IF	$Chipset >= 19		; IVB and above 
          Page "PSR feature"
            Link	"Close Table" , ".."
			
            Combo	$PSR_FullLink_Enable_01, "Full Link enable:", &Yes_No_List,
            Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
            Combo	$PSR_Require_AUX2Wakeup_01, "Require AUX to wake up:", &Yes_No_List,
            Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
							
            Combo	$PSR_Lines2Wait_B4LinkS3_01, "Lines to wait before link standby:", &wait_line_link,
            Help	"This field determines Lines to wait before link standby \n"
                    "Note: This is applicable only on Haswell \n"

           EditNum	$PSR_IdleFrames2Wait_01, "Idle frames to wait:", DEC,
           Help		"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"

           EditNum	$PSR_TP1_WaitTime_01, "TP1 WakeUp Time:", DEC,
           Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
				"TP1 wake up time in multiples of 100us \n"
		
           EditNum	$PSR_TP_2_3_WaitTime_01, "TP2/TP3 WakeUp Time:", DEC,
           Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
				"TP2/TP3 wake up time in multiples of 100us"
				
         EndPage		; PSR feature
       #ENDIF			; IVB and above 
     #ENDIF	; $LVDS_Config == 3 ; eDP

      #IF	0 ; $LVDS_Config == 3 ; eDP
        Page "Black Frame Insertion Parameters"
          Link	"Close Table" , ".."

          Combo	$BFI_Enable_01, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
          Help	"This feature allows the enabling of Black frame Insertion in Driver."

          Combo	$Brightness_Enable_01, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
          Help	"This feature allows the enabling of brightness adjustment in CUI."

          EditNum	$Brightness_non_BFI_01, " Brightness % in when BFI not enabled:", DEC,
          Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
        EndPage
      #ENDIF	; eDP

    EndPage
    ;==============================================================================
    ; Page - Panel #2 (800x600 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------

    Page "Panel #2 "

      Title	"Local Flat Panel (LFP) Size"

      
      EditText   $Panel_Name_02, "LFP panel name:", 
      Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "
      
      
      EditNum	$Panel_Width_02, "LFP Width:", DEC,
      Help	"This value specifies the LFP pixel width for this panel "
      "type."

      EditNum	$Panel_Height_02, "LFP Height:", DEC,
      Help	"This value specifies the LFP pixel height (number of scan "
      "lines) for this panel type."
      
	 Combo    $eDP_VSwingPreEmph_2, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
	 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

     
      Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      
      Link "DTD Timings Table" , "DTD Timings"
      Link "LFP PnP ID Table" , "LFP PnP ID"
      Link "Backlight Control Parameters" , "Backlight Control Parameters"
      Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
   	    Link "Chromaticity Control" , "Chromaticity Control"

      #IF	0; $LVDS_Config == 3; Int eDP
        Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
      #ENDIF	; IVM OR IVD


      #IF	$LVDS_Config == 1 ; Int LVDS
        Combo	$Int_LVDS_Panel_2_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
        Help	"SETTINGS :\r\n"
        "Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
        "Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
        "Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Co        ntrol with respect to Channel Selection.\r\n"
        "Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
        "			   X >= 1280, Check Y-Resolution.\r\n"
        "Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
        "			  Y > 800, Set LVDS for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS


      #IF	$LVDS_Config == 1 
        Combo	$INT_Panel_Color_Depth02, "Panel Color Depth:", &Panel_Color_Depth_List,
        Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 


      #IF	$LVDS_Config == 3 ; eDP
        Combo	$eDP_Panel_Color_Depth_02, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
        Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      

      #IF	$LVDS_Config == 1 ; Int LVDS
        Title	"Spread Spectrum Clock Features"
        Combo	$Enable_SSC02, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
        Help	"This feature when enabled will instruct software to use the "
        "external Spread Spectrum input clock as the internal LFP "
        "PLL reference clock.  Otherwise, when disabled, the internal "
        "reference clock will be used as the internal LFP PLL "
        "reference clock ignoring any Spread Spectrum input clock.\r\n"
        "\r\n"
        "Note: When enabling SSC option, please make sure that the hardware/"
        "system BIOS has enabled this feature in the chipset platform. "
        "The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
        "option must match the actual SSC frequency determined by platform "
        "hardware and/or system BIOS."
        "\r\n"
        "Note: This option is for internal LFP only.\r\n"
        "\r\n"
        "Note: Currently, this feature will also replace the CRT PLL "
        "reference clock on the same pipe that may cause CRT jitter.  "
        "Ideas to help this situation are to remove single pipe "
        "simultaneous display combinations (dual display twin) or use "
        "the 'Disable SSC in Dual Display Twin' option to "
        "automatically switch back to internal reference clock when "
        "entering a dual display twin display combination."
        Combo	$SSC_Freq02, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
        Help	"The SSC frequency selected must match the actual SSC frequency "
        "determined by platform hardware and/or system BIOS.\r\n"
        Combo	$Disable_SSC_DDT02, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
        Help	"This feature allows a selectable option for OEMs to disable "
        "Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
        "Pipe Simultaneous mode.\r\n"
        "\r\n"
        "Note: Disabling means that SSC will not be enabled while "
        "Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
        "when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP

        Title	"eDP Spread Spectrum Clock Features"
        Combo	$Enable_SSC02, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
        Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
     
	  #ENDIF	; $LVDS_Config == 1 ; Int LVDS


      #IF	$LVDS_Config == 3 ; eDP
        Combo	$edp_S3D_Feature_02, "  Steroscopic 3D:", &Disabled_Enabled_List,
        Help	"This feature allows a selectable option to determine whether "
        "to enable/disable S3D feature in driver.\r\n"
      #ENDIF	; $LVDS_Config == 3 ; eDP

      Title	"DPS Panel Type Features (Mobile only)"
      Combo	$DPS_Panel_Type_02, "  DPS Panel Type:", &DPS_Panel_Type_List,
      Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
      "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
      "which reduces display Power\r\n"
      "SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
      "rate will not adversely impact the user experience\r\n"
      "Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
      "rate will not adversely impact the user experience.Implements seamless refresh\r\n"
      "rate switching, which eliminates the screen blink that occurred\r\n" 
      "during the refresh rate transitions\r\n"

      #IF	$Chipset >= 17 && $Chipset <= 18	; SNB

        #IF	$LVDS_Config == 3 ; eDP
          Combo	$eDP_sDRRS_MSA_Delay_02, "  MSA Timing Delay:", &MSA_TimingDelay_List,
          Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
          "The sDRRS timing switch shall occur on same line as the MSA\r\n"
          "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
          "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
          "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
          "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
        #ENDIF	; $LVDS_Config == 3 ; eDP

      #ENDIF	; SNB

      Title	"BackLight Technology Type Features (Mobile only)"
      Combo	$Blt_Control_02, "  BackLight Technology:", &Blt_Control_Type_List,
      Help     "This feature allows OEM to select the Backlight Technology.\r\n "
	
     #IF	$Chipset >= 19		; IVB and above 
        #IF  $LVDS_Config == 3	; Int eDP
		  Title " "
                  Link "PSR feature" ,"PSR feature"
	#ENDIF		; eDP
     #ENDIF		; IVB Mobile and above

      #IF	$LVDS_Config == 1 ; Int LVDS
        Page "Panel Power Sequencing"
          
          Link	"Close Table" , ".."
          
          EditNum	$Power_On_Backlight_Enable_Delay_02, "  Power On to Backlight Enable Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for delay of Power on to backlight enable."

          EditNum	$PowerUpDelay_02, "  Panel Power Up Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for panel Power up delay. Note: This value "
          "is typically T1 + T2."

          EditNum	$Power_Backlight_Off_Power_Down_Delay_02, "  Power Backlight Off to Power Down Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for Power backlight off to Power down delay."

          EditNum	$PowerDownDelay_02, "  Panel Power Down Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for Power down delay."
          
          EditNum	$PowerCycleDelay_02, "  Panel Power Cycle Delay Time:", DEC,
          Help	"This feature specifies the panel Power sequencing time "
          "for Power Cycle delay."
          "\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
          "to have a delay of 400ms, programming value should be 5 instead of 4"
          
        EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
        Page	"Panel Power Sequencing"
          Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
        EndPage
      #ENDIF	; $LVDS_Config == 1 ; iLVDS

      
      Page "DTD Timings"

        Link	"Close Table" , ".."

        Table	$DVO_Tbl_02 " DTD Timings Values",
        Column "Timings" , 1 byte , EHEX,
        Help	"This feature allows for the definition of the DTD "
        "timings parameters related to the LFP.  The "
        "table is the 18-byte DTD structure defined in the "
        "VESA EDID version 1.x.\r\n"  
        "\r\n"
        "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
        "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
        "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
        "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
        "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
        "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
        "\tByte6 \t: Vertical Active in lines, LSB\r\n"
        "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
        "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
        "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
        "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
        "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
        "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
        "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
        "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
        "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
        "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
        "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
        "\tByte13 \t: Horizontal Image Size, LSB\r\n"
        "\tByte14 \t: Vertical Image Size, LSB\r\n"
        "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
        "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
        "\tByte16 \t: Horizontal Border in pixels\r\n"
        "\tByte17 \t: Vertical Border in lines\r\n"
        "\tByte18 \t: Flags:\r\n"
        "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
        "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
        "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
        "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
        "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
        "\t   \t:   Bit 0:   0 = Reserved"
      EndPage

      Page "LFP PnP ID"

        Link	"Close Table" , ".."

        Table	$LVDS_PnP_ID_02 " LFP PnP ID Values",
        Column "PnP ID" , 1 byte , EHEX,
        Help	"This feature allows the 10 bytes of EDID Vendor / "
        "Product ID starting at offset 08h to be used as a "
        "PnP ID.\r\n"
        "\r\n"
        " Table Definition:\r\n"
        "  Word:  ID Manufacturer Name\r\n"
        "  Word:  ID Product Code\r\n"
        "  DWord: ID Serial Number\r\n"
        "  Byte:  Week of Manufacture\r\n"
        "  Byte:  Year of Manufacture"
      EndPage

      Page "Backlight Control Parameters"

        Link	"Close Table" , ".."

        Combo	$BLC_Inv_Type_2, "  Inverter Type:", &Inv_Type_List,
        Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

        Combo	$BLC_Inv_Polarity_2, "  Inverter Polarity:", &Inv_Polarity_List,
        Help	"This feature allows the backlight inverter polarity "
        "to be specified.\r\n"
        "\r\n"
        "Normal means 0 value is minimum brightness.\r\n"
        "Inverted means 0 value is maximum brightness."

        EditNum	$BLC_Min_Brightness_2, "  Minimum Brightness:", DEC,
        Help	"This feature allows defining the absolute minimum "
        "backlight brightness setting.  The graphics driver "
        "will never decrease the backlight less than this "
        "value.  The value must be specified using normal "
        "polarity semantics."

        EditNum	$POST_BL_Brightness_02, "  POST Brightness:", DEC,
        Help	"This feature is used only by video BIOS to set initial "
        "brightness level at POST. \r\n"
        "This is configurable field of 0-255. "
        "Value of 0 inidicates Zero brightness, 255 indicates maximum "
        "brightness."

        EditNum	$PWM_Frequency_2, "  PWM Inverter Frequency (Hz):", DEC,
        Help	"This feature allows for the definition of the "
        "frequency needed for PWM Inverter.\r\n"
        "\r\n"
        "Note: The frequency range, entered as a decimal "
        "number, for the integrated PWM is 200Hz - 40KHz."

          ;          Combo	$BLC_GPIO_Pins_2, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
          ;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
          ;          "this device."

          ;          Combo	$BLC_GMBus_Speed_2, "  I2C Bus Frequency:", &GMBus_Speed_List,
          ;          Help	"Selects the I2C bus frequency to use when "
          ;          "communicating to this device."

          ;          EditNum	$BLC_I2C_Addr_2, "  I2C Device Address:", HEX,
          ;          Help	"Selects the I2C device address for communication to "
          ;          "this backlight inverter.  The device address should "
          ;          "be in 8-bit format with the slave address assigned to "
          ;          "bits 7:1 and bit 0 cleared.  For example, the slave "
          ;          "address 0101100b would be stated here as 58h."

          ;          EditNum	$BLC_Brightness_Cmd_2, "  I2C Device, Display Brightness Command Code:", HEX,
          ;          Help	"Selects the command code (register index) for setting "
          ;          "the backlight brightness."
        EndPage
	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_2, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_2, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_2, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_2, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_2, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_2, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_2, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_2, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_2, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_2, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_2, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_2, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

      #IF	$LVDS_Config == 3 ; eDP
        Page "eDP Fast Link Training Configuration Parameters"

          Link	"Close Table" , ".."
          
          Combo	$Fast_Link_Training_Supported_02, "  Is Fast Link Training feature supported:", &No_Yes_List,
          Help	"This feature allows for the selection of the "
          "Fast Link Training feature is to be enabled or disabled."
          
          Combo	$eDP_Link_DataRate_02, "  Data Rate:", &eDP_Link_DataRate_List,
          Help	"This feature allows for the selection of the "
          "Data Rate for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training."

          Combo	$eDP_Link_LaneCount_02, "  Lane Count:", &eDP_Link_LaneCount_List,
          Help	"This feature allows for the selection of the "
          "Lane Count (Port Width) for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training."

          Combo	$eDP_Link_PreEmp_02, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
         Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
          
		Combo	$eDP_Link_VSwing_02, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
          
        EndPage
     
       #IF	$Chipset >= 19		; IVB and above 
          Page "PSR feature"
            Link	"Close Table" , ".."
			
             Combo	$PSR_FullLink_Enable_02, "Full Link enable:", &Yes_No_List,
             Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
             Combo	$PSR_Require_AUX2Wakeup_02, "Require AUX to wake up:", &Yes_No_List,
             Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
             Combo	$PSR_Lines2Wait_B4LinkS3_02, "Lines to wait before link standby:", &wait_line_link,
             Help	"This field determines Lines to wait before link standby \n"
                    "Note: This is applicable only on Haswell \n"

            EditNum	$PSR_IdleFrames2Wait_02, "Idle frames to wait:", DEC,
            Help	"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"

            EditNum	$PSR_TP1_WaitTime_02, "TP1 WakeUp Time:", DEC,
            Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
				"TP1 wake up time in multiples of 100us \n"
		
            EditNum	$PSR_TP_2_3_WaitTime_02, "TP2/TP3 WakeUp Time:", DEC,
            Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
			"TP2/TP3 wake up time in multiples of 100us"
			
         EndPage		; PSR feature
      #ENDIF			; IVB Mobile and above
    #ENDIF			; $LVDS_Config == 3 ; eDP

      #IF	0; $LVDS_Config == 3 ; eDP
        Page "Black Frame Insertion Parameters"

          Link	"Close Table" , ".."

          Combo	$BFI_Enable_02, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
          Help	"This feature allows the enabling of Black frame Insertion in Driver."

          Combo	$Brightness_Enable_02, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
          Help	"This feature allows the enabling of brightness adjustment in CUI."

          EditNum	$Brightness_non_BFI_02, " Brightness % in when BFI not enabled:", DEC,
          Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
        EndPage
      #ENDIF	; eDP

    EndPage
    ;==============================================================================
    ; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters
    ;------------------------------------------------------------------------------

    Page "Panel #3 "

      Title	"Local Flat Panel (LFP) Size"

      
      EditText   $Panel_Name_03, "LFP panel name:", 
      Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "
      

      EditNum	$Panel_Width_03, "LFP Width:", DEC,
      Help	"This value specifies the LFP pixel width for this panel "
      "type."

      EditNum	$Panel_Height_03, "LFP Height:", DEC,
      Help	"This value specifies the LFP pixel height (number of scan "
      "lines) for this panel type."
      
	
	Combo    $eDP_VSwingPreEmph_3, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
	 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

      
      Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
      
      Link "DTD Timings Table" , "DTD Timings"
      Link "LFP PnP ID Table" , "LFP PnP ID"
      Link "Backlight Control Parameters" , "Backlight Control Parameters"
      Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

      #IF	0; $LVDS_Config == 3; Int eDP
        Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
      #ENDIF	; IVM OR IVD


      #IF	$LVDS_Config == 1 ; Int LVDS
        Combo	$Int_LVDS_Panel_3_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
        Help	"SETTINGS :\r\n"
        "Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
        "Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
        "Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Co        ntrol with respect to Channel Selection.\r\n"
        "Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
        "			   X >= 1280, Check Y-Resolution.\r\n"
        "Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
        "			  Y > 800, Set LVDS for Dual Channel.\r\n"
      #ENDIF	; $LVDS_Config == 1 ; Int LVDS


      #IF	$LVDS_Config == 1 
        Combo	$INT_Panel_Color_Depth03, "Panel Color Depth:", &Panel_Color_Depth_List,
        Help	"This feature specifies the color depth of the integrated LFP panel used. "
      #ENDIF	; $LVDS_Config == 1 


      #IF	$LVDS_Config == 3 ; eDP
        Combo	$eDP_Panel_Color_Depth_03, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
        Help	"This feature specifies the color depth of eDP panel used. "
      #ENDIF	; $LVDS_Config == 3 ; eDP

      

      #IF	$LVDS_Config == 1 ; Int LVDS
        Title	"Spread Spectrum Clock Features"
        Combo	$Enable_SSC03, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
        Help	"This feature when enabled will instruct software to use the "
        "external Spread Spectrum input clock as the internal LFP "
        "PLL reference clock.  Otherwise, when disabled, the internal "
        "reference clock will be used as the internal LFP PLL "
        "reference clock ignoring any Spread Spectrum input clock.\r\n"
        "\r\n"
        "Note: When enabling SSC option, please make sure that the hardware/"
        "system BIOS has enabled this feature in the chipset platform. "
        "The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
        "option must match the actual SSC frequency determined by platform "
        "hardware and/or system BIOS."
        "\r\n"
        "Note: This option is for internal LFP only.\r\n"
        "\r\n"
        "Note: Currently, this feature will also replace the CRT PLL "
        "reference clock on the same pipe that may cause CRT jitter.  "
        "Ideas to help this situation are to remove single pipe "
        "simultaneous display combinations (dual display twin) or use "
        "the 'Disable SSC in Dual Display Twin' option to "
        "automatically switch back to internal reference clock when "
        "entering a dual display twin display combination."
        Combo	$SSC_Freq03, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
        Help	"The SSC frequency selected must match the actual SSC frequency "
        "determined by platform hardware and/or system BIOS.\r\n"
        Combo	$Disable_SSC_DDT03, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
        Help	"This feature allows a selectable option for OEMs to disable "
        "Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
        "Pipe Simultaneous mode.\r\n"
        "\r\n"
        "Note: Disabling means that SSC will not be enabled while "
        "Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
        "when DDT is exited."
      #ELSEIF	$LVDS_Config == 3 ; eDP
    
	    Title	"eDP Spread Spectrum Clock Features"
        Combo	$Enable_SSC03, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
        Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
    
	  #ENDIF	; $LVDS_Config == 1 ; Int LVDS


      #IF	$LVDS_Config == 3 ; eDP
        Combo	$edp_S3D_Feature_03, "  Steroscopic 3D:", &Disabled_Enabled_List,
        Help	"This feature allows a selectable option to determine whether "
        "to enable/disable S3D feature in driver.\r\n"
      #ENDIF	; SNB and above

      Title	"DPS Panel Type Features (Mobile only)"
      Combo	$DPS_Panel_Type_03, "  DPS Panel Type:", &DPS_Panel_Type_List,
      Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
      "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
      "which reduces display Power\r\n"
      "SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
      "rate will not adversely impact the user experience\r\n"
      "Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
      "rate will not adversely impact the user experience.Implements seamless refresh\r\n"
      "rate switching, which eliminates the screen blink that occurred\r\n" 
      "during the refresh rate transitions\r\n"

      #IF	$Chipset >= 17 && $Chipset <= 18	; SNB

        #IF	$LVDS_Config == 3 ; eDP
          Combo	$eDP_sDRRS_MSA_Delay_03, "  MSA Timing Delay:", &MSA_TimingDelay_List,
          Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
          "The sDRRS timing switch shall occur on same line as the MSA\r\n"
          "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
          "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
          "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
          "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
        #ENDIF	; $LVDS_Config == 3 ; eDP

      #ENDIF	; SNB

      Title	"BackLight Technology Type Features (Mobile only)"
      Combo	$Blt_Control_03, "  BackLight Technology:", &Blt_Control_Type_List,
      Help     "This feature allows OEM to select the Backlight Technology.\r\n "
    #ENDIF    ; Mobile
     
      #IF	$Chipset >= 19		; IVB and above 
     	  #IF  $LVDS_Config == 3	; Int eDP
		  Title " "
                  Link "PSR feature" ,"PSR feature"
	  #ENDIF			; eDP
      #ENDIF				; IVB Mobile and above
	

    #IF	$LVDS_Config == 1 ; Int LVDS
      Page "Panel Power Sequencing"
        
        Link	"Close Table" , ".."
        
        EditNum	$Power_On_Backlight_Enable_Delay_03, "  Power On to Backlight Enable Delay Time:", DEC,
        Help	"This feature specifies the panel Power sequencing time "
        "for delay of Power on to backlight enable."

        EditNum	$PowerUpDelay_03, "  Panel Power Up Delay Time:", DEC,
        Help	"This feature specifies the panel Power sequencing time "
        "for panel Power up delay. Note: This value "
        "is typically T1 + T2."

        EditNum	$Power_Backlight_Off_Power_Down_Delay_03, "  Power Backlight Off to Power Down Delay Time:", DEC,
        Help	"This feature specifies the panel Power sequencing time "
        "for Power backlight off to Power down delay."

        EditNum	$PowerDownDelay_03, "  Panel Power Down Delay Time:", DEC,
        Help	"This feature specifies the panel Power sequencing time "
        "for Power down delay."
        
        EditNum	$PowerCycleDelay_03, "  Panel Power Cycle Delay Time:", DEC,
        Help	"This feature specifies the panel Power sequencing time "
        "for Power Cycle delay."
        "\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
        "to have a delay of 400ms, programming value should be 5 instead of 4"
        
      EndPage
    #ELSEIF	$LVDS_Config == 3 ; eDP
      Page	"Panel Power Sequencing"
        Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
      EndPage
    #ENDIF	; $LVDS_Config == 1 ; iLVDS

    

    Page "DTD Timings"

      Link	"Close Table" , ".."

      Table	$DVO_Tbl_03 " DTD Timings Values",
      Column "Timings" , 1 byte , EHEX,
      Help	"This feature allows for the definition of the DTD "
      "timings parameters related to the LFP.  The "
      "table is the 18-byte DTD structure defined in the "
      "VESA EDID version 1.x.\r\n"  
      "\r\n"
      "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
      "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
      "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
      "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
      "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
      "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
      "\tByte6 \t: Vertical Active in lines, LSB\r\n"
      "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
      "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
      "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
      "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
      "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
      "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
      "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
      "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
      "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
      "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
      "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
      "\tByte13 \t: Horizontal Image Size, LSB\r\n"
      "\tByte14 \t: Vertical Image Size, LSB\r\n"
      "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
      "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
      "\tByte16 \t: Horizontal Border in pixels\r\n"
      "\tByte17 \t: Vertical Border in lines\r\n"
      "\tByte18 \t: Flags:\r\n"
      "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
      "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
      "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
      "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
      "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
      "\t   \t:   Bit 0:   0 = Reserved"
    EndPage

    Page "LFP PnP ID"

      Link	"Close Table" , ".."

      Table	$LVDS_PnP_ID_03 " LFP PnP ID Values",
      Column "PnP ID" , 1 byte , EHEX,
      Help	"This feature allows the 10 bytes of EDID Vendor / "
      "Product ID starting at offset 08h to be used as a "
      "PnP ID.\r\n"
      "\r\n"
      " Table Definition:\r\n"
      "  Word:  ID Manufacturer Name\r\n"
      "  Word:  ID Product Code\r\n"
      "  DWord: ID Serial Number\r\n"
      "  Byte:  Week of Manufacture\r\n"
      "  Byte:  Year of Manufacture"
    EndPage

    Page "Backlight Control Parameters"

      Link	"Close Table" , ".."

      Combo	$BLC_Inv_Type_3, "  Inverter Type:", &Inv_Type_List,
      Help	"This feature selects the "
			"Backlight Inverter type that is used to "
			"control backlight brightness of LFP.  When "
			"PWM is selected, the driver and GOP/VBIOS control "
			"the backlight brightness via integrated PWM "
			"solution for the chipsets.  When None/External is "
			"selected, the system BIOS controls the backlight "
			"brightness via external solution."

      Combo	$BLC_Inv_Polarity_3, "  Inverter Polarity:", &Inv_Polarity_List,
      Help	"This feature allows the backlight inverter polarity "
      "to be specified.\r\n"
      "\r\n"
      "Normal means 0 value is minimum brightness.\r\n"
      "Inverted means 0 value is maximum brightness."

      EditNum	$BLC_Min_Brightness_3, "  Minimum Brightness:", DEC,
      Help	"This feature allows defining the absolute minimum "
      "backlight brightness setting.  The graphics driver "
      "will never decrease the backlight less than this "
      "value.  The value must be specified using normal "
      "polarity semantics."

      EditNum	$POST_BL_Brightness_03, "  POST Brightness:", DEC,
      Help	"This feature is used only by video BIOS to set initial "
      "brightness level at POST. \r\n"
      "This is configurable field of 0-255. "
      "Value of 0 inidicates Zero brightness, 255 indicates maximum "
      "brightness."

      EditNum	$PWM_Frequency_3, "  PWM Inverter Frequency (Hz):", DEC,
      Help	"This feature allows for the definition of the "
      "frequency needed for PWM Inverter.\r\n"
      "\r\n"
      "Note: The frequency range, entered as a decimal "
      "number, for the integrated PWM is 200Hz - 40KHz."

        ;          Combo	$BLC_GPIO_Pins_3, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
        ;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
        ;          "this device."

        ;          Combo	$BLC_GMBus_Speed_3, "  I2C Bus Frequency:", &GMBus_Speed_List,
        ;          Help	"Selects the I2C bus frequency to use when "
        ;          "communicating to this device."

        ;          EditNum	$BLC_I2C_Addr_3, "  I2C Device Address:", HEX,
        ;          Help	"Selects the I2C device address for communication to "
        ;          "this backlight inverter.  The device address should "
        ;          "be in 8-bit format with the slave address assigned to "
        ;          "bits 7:1 and bit 0 cleared.  For example, the slave "
        ;          "address 0101100b would be stated here as 58h."

        ;          EditNum	$BLC_Brightness_Cmd_3, "  I2C Device, Display Brightness Command Code:", HEX,
        ;          Help	"Selects the command code (register index) for setting "
        ;          "the backlight brightness."
      EndPage


 	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_3, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_3, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_3, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_3, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_3, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_3, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_3, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_3, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_3, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_3, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_3, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_3, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

    #IF	$LVDS_Config == 3 ; eDP
      Page "eDP Fast Link Training Configuration Parameters"

        Link	"Close Table" , ".."
        
        Combo	$Fast_Link_Training_Supported_03, "  Is Fast Link Training feature supported:", &No_Yes_List,
          Help	"This feature allows for the selection of the "
          "Fast Link Training feature is to be enabled or disabled."
        
        Combo	$eDP_Link_DataRate_03, "  Data Rate:", &eDP_Link_DataRate_List,
        Help	"This feature allows for the selection of the "
        "Data Rate for the embedded DP link. It will be used if the "
        "sink indicates that no aux handshake is required during link training."

        Combo	$eDP_Link_LaneCount_03, "  Lane Count:", &eDP_Link_LaneCount_List,
        Help	"This feature allows for the selection of the "
        "Lane Count (Port Width) for the embedded DP link. It will be used if the "
        "sink indicates that no aux handshake is required during link training."

        Combo	$eDP_Link_PreEmp_03, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
         Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
    	Combo	$eDP_Link_VSwing_03, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
		
	      
      EndPage
      
        #IF	$Chipset >= 19		; IVB and above 
          Page "PSR feature"
            Link	"Close Table" , ".."
			
             Combo	$PSR_FullLink_Enable_03, "Full Link enable:", &Yes_No_List,
             Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
             Combo	$PSR_Require_AUX2Wakeup_03, "Require AUX to wake up:", &Yes_No_List,
             Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
             Combo	$PSR_Lines2Wait_B4LinkS3_03, "Lines to wait before link standby:", &wait_line_link,
             Help	"This field determines Lines to wait before link standby \n"
                    "Note: This is applicable only on Haswell \n"

            EditNum	$PSR_IdleFrames2Wait_03, "Idle frames to wait:", DEC,
            Help	"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"

            EditNum	$PSR_TP1_WaitTime_03, "TP1 WakeUp Time:", DEC,
            Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
					"TP1 wake up time in multiples of 100us \n"
		
            EditNum	$PSR_TP_2_3_WaitTime_03, "TP2/TP3 WakeUp Time:", DEC,
            Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
					"TP2/TP3 wake up time in multiples of 100us"

         EndPage	; PSR feature
       #ENDIF		; IVB Mobile and above
    #ENDIF		; $LVDS_Config == 3 ; eDP


    #IF	0 ;$LVDS_Config == 3 ; eDP
      Page "Black Frame Insertion Parameters"
        Link	"Close Table" , ".."

        Combo	$BFI_Enable_03, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
        Help	"This feature allows the enabling of Black frame Insertion in Driver."

        Combo	$Brightness_Enable_03, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
        Help	"This feature allows the enabling of brightness adjustment in CUI."

        EditNum	$Brightness_non_BFI_03, " Brightness % in when BFI not enabled:", DEC,
        Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
      EndPage
    #ENDIF	; eDP

  EndPage
  ;==============================================================================
  ; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters
  ;------------------------------------------------------------------------------

  Page "Panel #4 "

    Title	"Local Flat Panel (LFP) Size"

    
    EditText   $Panel_Name_04, "LFP panel name:", 
    Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "
    

    EditNum	$Panel_Width_04, "LFP Width:", DEC,
    Help	"This value specifies the LFP pixel width for this panel "
    "type."

    EditNum	$Panel_Height_04, "LFP Height:", DEC,
    Help	"This value specifies the LFP pixel height (number of scan "
    "lines) for this panel type."
    

	Combo    $eDP_VSwingPreEmph_4, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
	 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

	  
    Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
    
    Link "DTD Timings Table" , "DTD Timings"
    Link "LFP PnP ID Table" , "LFP PnP ID"
    Link "Backlight Control Parameters" , "Backlight Control Parameters"
    Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

    #IF	0; $LVDS_Config == 3; Int eDP
      Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
    #ENDIF	; IVM OR IVD


    #IF	$LVDS_Config == 1 ; Int LVDS
      Combo	$Int_LVDS_Panel_4_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
      Help	"SETTINGS :\r\n"
      "Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
      "Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
      "Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Co        ntrol with respect to Channel Selection.\r\n"
      "Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
      "			   X >= 1280, Check Y-Resolution.\r\n"
      "Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
      "			  Y > 800, Set LVDS for Dual Channel.\r\n"
    #ENDIF	; $LVDS_Config == 1 ; Int LVDS


    #IF	$LVDS_Config == 1 
      Combo	$INT_Panel_Color_Depth04, "Panel Color Depth:", &Panel_Color_Depth_List,
      Help	"This feature specifies the color depth of the integrated LFP panel used. "
    #ENDIF	; $LVDS_Config == 1 


    #IF	$LVDS_Config == 3 ; eDP
      Combo	$eDP_Panel_Color_Depth_04, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
      Help	"This feature specifies the color depth of eDP panel used. "
    #ENDIF	; $LVDS_Config == 3 ; eDP

    

    #IF	$LVDS_Config == 1 ; Int LVDS
      Title	"Spread Spectrum Clock Features"
      Combo	$Enable_SSC04, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help	"This feature when enabled will instruct software to use the "
      "external Spread Spectrum input clock as the internal LFP "
      "PLL reference clock.  Otherwise, when disabled, the internal "
      "reference clock will be used as the internal LFP PLL "
      "reference clock ignoring any Spread Spectrum input clock.\r\n"
      "\r\n"
      "Note: When enabling SSC option, please make sure that the hardware/"
      "system BIOS has enabled this feature in the chipset platform. "
      "The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
      "option must match the actual SSC frequency determined by platform "
      "hardware and/or system BIOS."
      "\r\n"
      "Note: This option is for internal LFP only.\r\n"
      "\r\n"
      "Note: Currently, this feature will also replace the CRT PLL "
      "reference clock on the same pipe that may cause CRT jitter.  "
      "Ideas to help this situation are to remove single pipe "
      "simultaneous display combinations (dual display twin) or use "
      "the 'Disable SSC in Dual Display Twin' option to "
      "automatically switch back to internal reference clock when "
      "entering a dual display twin display combination."
      Combo	$SSC_Freq04, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
      Help	"The SSC frequency selected must match the actual SSC frequency "
      "determined by platform hardware and/or system BIOS.\r\n"
      Combo	$Disable_SSC_DDT04, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
      Help	"This feature allows a selectable option for OEMs to disable "
      "Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
      "Pipe Simultaneous mode.\r\n"
      "\r\n"
      "Note: Disabling means that SSC will not be enabled while "
      "Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
      "when DDT is exited."
    #ELSEIF	$LVDS_Config == 3 ; eDP

      Title	"eDP Spread Spectrum Clock Features"
      Combo	$Enable_SSC04, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
      Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "
  
    #ENDIF	; $LVDS_Config == 1 ; Int LVDS


    #IF	$LVDS_Config == 3 ; eDP
      Combo	$edp_S3D_Feature_04, "  Steroscopic 3D:", &Disabled_Enabled_List,
      Help	"This feature allows a selectable option to determine whether "
      "to enable/disable S3D feature in driver.\r\n"
    #ENDIF	; $LVDS_Config == 3 ; eDP

    
    Title	"DPS Panel Type Features (Mobile only)"
    Combo	$DPS_Panel_Type_04, "  DPS Panel Type:", &DPS_Panel_Type_List,
    Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
    "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
    "which reduces display Power\r\n"
    "SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
    "rate will not adversely impact the user experience\r\n"
    "Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
    "rate will not adversely impact the user experience.Implements seamless refresh\r\n"
    "rate switching, which eliminates the screen blink that occurred\r\n" 
    "during the refresh rate transitions\r\n"

    #IF	$Chipset >= 17 && $Chipset <= 18	; SNB

      #IF	$LVDS_Config == 3 ; eDP
        Combo	$eDP_sDRRS_MSA_Delay_04, "  MSA Timing Delay:", &MSA_TimingDelay_List,
        Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
        "The sDRRS timing switch shall occur on same line as the MSA\r\n"
        "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
        "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
        "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
        "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
      #ENDIF	; $LVDS_Config == 3 ; eDP

    #ENDIF	; SNB

    
    Title	"BackLight Technology Type Features (Mobile only)"
    Combo	$Blt_Control_04, "  BackLight Technology:", &Blt_Control_Type_List,
    Help     "This feature allows OEM to select the Backlight Technology.\r\n "
  #ENDIF    ; Mobile
     

      #IF	$Chipset >= 19		; IVB and above 
     	  #IF  $LVDS_Config == 3	; Int eDP
		  Title " "
                  Link "PSR feature" ,"PSR feature"
	  #ENDIF			; eDP
      #ENDIF				; IVB Mobile and above

	
     #IF	$LVDS_Config == 1 ; Int LVDS
          Page "Panel Power Sequencing"
            
            Link	"Close Table" , ".."
            
            EditNum	$Power_On_Backlight_Enable_Delay_04, "  Power On to Backlight Enable Delay Time:", DEC,
            Help	"This feature specifies the panel Power sequencing time "
            "for delay of Power on to backlight enable."

      EditNum	$PowerUpDelay_04, "  Panel Power Up Delay Time:", DEC,
      Help	"This feature specifies the panel Power sequencing time "
      "for panel Power up delay. Note: This value "
      "is typically T1 + T2."

      EditNum	$Power_Backlight_Off_Power_Down_Delay_04, "  Power Backlight Off to Power Down Delay Time:", DEC,
      Help	"This feature specifies the panel Power sequencing time "
      "for Power backlight off to Power down delay."

      EditNum	$PowerDownDelay_04, "  Panel Power Down Delay Time:", DEC,
      Help	"This feature specifies the panel Power sequencing time "
      "for Power down delay."
      
      EditNum	$PowerCycleDelay_04, "  Panel Power Cycle Delay Time:", DEC,
      Help	"This feature specifies the panel Power sequencing time "
      "for Power Cycle delay."
      "\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
      "to have a delay of 400ms, programming value should be 5 instead of 4"
    EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
    Page	"Panel Power Sequencing"
      Link	"Close Table", ".."
			Combo	$eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
    EndPage
  #ENDIF	; $LVDS_Config == 1 ; iLVDS

  

  Page "DTD Timings"

    Link	"Close Table" , ".."

    Table	$DVO_Tbl_04 " DTD Timings Values",
    Column "Timings" , 1 byte , EHEX,
    Help	"This feature allows for the definition of the DTD "
    "timings parameters related to the LFP.  The "
    "table is the 18-byte DTD structure defined in the "
    "VESA EDID version 1.x.\r\n"  
    "\r\n"
    "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
    "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
    "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
    "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
    "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
    "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
    "\tByte6 \t: Vertical Active in lines, LSB\r\n"
    "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
    "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
    "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
    "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
    "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
    "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
    "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
    "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
    "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
    "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
    "\tByte13 \t: Horizontal Image Size, LSB\r\n"
    "\tByte14 \t: Vertical Image Size, LSB\r\n"
    "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
    "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
    "\tByte16 \t: Horizontal Border in pixels\r\n"
    "\tByte17 \t: Vertical Border in lines\r\n"
    "\tByte18 \t: Flags:\r\n"
    "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
    "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
    "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
    "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
    "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
    "\t   \t:   Bit 0:   0 = Reserved"
  EndPage

  Page "LFP PnP ID"

    Link	"Close Table" , ".."

    Table	$LVDS_PnP_ID_04 " LFP PnP ID Values",
    Column "PnP ID" , 1 byte , EHEX,
    Help	"This feature allows the 10 bytes of EDID Vendor / "
    "Product ID starting at offset 08h to be used as a "
    "PnP ID.\r\n"
    "\r\n"
    " Table Definition:\r\n"
    "  Word:  ID Manufacturer Name\r\n"
    "  Word:  ID Product Code\r\n"
    "  DWord: ID Serial Number\r\n"
    "  Byte:  Week of Manufacture\r\n"
    "  Byte:  Year of Manufacture"
  EndPage

  Page "Backlight Control Parameters"

    Link	"Close Table" , ".."

    Combo	$BLC_Inv_Type_4, "  Inverter Type:", &Inv_Type_List,
    Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

    Combo	$BLC_Inv_Polarity_4, "  Inverter Polarity:", &Inv_Polarity_List,
    Help	"This feature allows the backlight inverter polarity "
    "to be specified.\r\n"
    "\r\n"
    "Normal means 0 value is minimum brightness.\r\n"
    "Inverted means 0 value is maximum brightness."

    EditNum	$BLC_Min_Brightness_4, "  Minimum Brightness:", DEC,
    Help	"This feature allows defining the absolute minimum "
    "backlight brightness setting.  The graphics driver "
    "will never decrease the backlight less than this "
    "value.  The value must be specified using normal "
    "polarity semantics."

    EditNum	$POST_BL_Brightness_04, "  POST Brightness:", DEC,
    Help	"This feature is used only by video BIOS to set initial "
    "brightness level at POST. \r\n"
    "This is configurable field of 0-255. "
    "Value of 0 inidicates Zero brightness, 255 indicates maximum "
    "brightness."

    EditNum	$PWM_Frequency_4, "  PWM Inverter Frequency (Hz):", DEC,
    Help	"This feature allows for the definition of the "
    "frequency needed for PWM Inverter.\r\n"
    "\r\n"
    "Note: The frequency range, entered as a decimal "
    "number, for the integrated PWM is 200Hz - 40KHz."

      ;          Combo	$BLC_GPIO_Pins_4, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
      ;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
      ;          "this device."

      ;          Combo	$BLC_GMBus_Speed_4, "  I2C Bus Frequency:", &GMBus_Speed_List,
      ;          Help	"Selects the I2C bus frequency to use when "
      ;          "communicating to this device."

      ;          EditNum	$BLC_I2C_Addr_4, "  I2C Device Address:", HEX,
      ;          Help	"Selects the I2C device address for communication to "
      ;          "this backlight inverter.  The device address should "
      ;          "be in 8-bit format with the slave address assigned to "
      ;          "bits 7:1 and bit 0 cleared.  For example, the slave "
      ;          "address 0101100b would be stated here as 58h."

      ;          EditNum	$BLC_Brightness_Cmd_4, "  I2C Device, Display Brightness Command Code:", HEX,
      ;          Help	"Selects the command code (register index) for setting "
      ;          "the backlight brightness."
  EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_4, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_4, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_4, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_4, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_4, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_4, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_4, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_4, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_4, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_4, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_4, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_4, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

  #IF	$LVDS_Config == 3 ; eDP
    Page "eDP Fast Link Training Configuration Parameters"
      Link	"Close Table" , ".."
      
      Combo	$Fast_Link_Training_Supported_04, "  Is Fast Link Training feature supported:", &No_Yes_List,
          Help	"This feature allows for the selection of the "
          "Fast Link Training feature is to be enabled or disabled."
      Combo	$eDP_Link_DataRate_04, "  Data Rate:", &eDP_Link_DataRate_List,
      Help	"This feature allows for the selection of the "
      "Data Rate for the embedded DP link. It will be used if the "
      "sink indicates that no aux handshake is required during link training."

      Combo	$eDP_Link_LaneCount_04, "  Lane Count:", &eDP_Link_LaneCount_List,
      Help	"This feature allows for the selection of the "
      "Lane Count (Port Width) for the embedded DP link. It will be used if the "
      "sink indicates that no aux handshake is required during link training."

      Combo	$eDP_Link_PreEmp_04, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
      Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
      
     		Combo	$eDP_Link_VSwing_04, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
			Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
		
          
       EndPage
    
	  #IF	$Chipset >= 19		; IVB and above 
          Page "PSR feature"
            Link	"Close Table" , ".."
			
            Combo	$PSR_FullLink_Enable_04, "  Full Link enable:", &Yes_No_List,
            Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
            Combo	$PSR_Require_AUX2Wakeup_04, "Require AUX to wake up:", &Yes_No_List,
            Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
            Combo	$PSR_Lines2Wait_B4LinkS3_04, " Lines to wait before link standby:", &wait_line_link,
            Help	"This field determines Lines to wait before link standby \n"
                    "Note: This is applicable only on Haswell \n"

             EditNum	$PSR_IdleFrames2Wait_04, "Idle frames to wait:", DEC,
             Help	"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"
             EditNum	$PSR_TP1_WaitTime_04, "TP1 WakeUp Time:", DEC,
             Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
					"TP1 wake up time in multiples of 100us \n"
		
             EditNum	$PSR_TP_2_3_WaitTime_04, "TP2/TP3 WakeUp Time:", DEC,
             Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
					"TP2/TP3 wake up time in multiples of 100us"

         EndPage		; PSR feature
       #ENDIF			; IVB Mobile and above
   #ENDIF			; $LVDS_Config == 3 ; eDP

  #IF	0; $LVDS_Config == 3 ; eDP
    Page "Black Frame Insertion Parameters"
      Link	"Close Table" , ".."

      Combo	$BFI_Enable_04, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
      Help	"This feature allows the enabling of Black frame Insertion in Driver."

      Combo	$Brightness_Enable_04, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
      Help	"This feature allows the enabling of brightness adjustment in CUI."

      EditNum	$Brightness_non_BFI_04, " Brightness % in when BFI not enabled:", DEC,
      Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
    EndPage
  #ENDIF	; eDP

EndPage
;==============================================================================
; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #5 "

  Title	"Local Flat Panel (LFP) Size"

  
  EditText   $Panel_Name_05, "LFP panel name:", 
  Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "
  

  EditNum	$Panel_Width_05, "LFP Width:", DEC,
  Help	"This value specifies the LFP pixel width for this panel "
  "type."

  EditNum	$Panel_Height_05, "LFP Height:", DEC,
  Help	"This value specifies the LFP pixel height (number of scan "
  "lines) for this panel type."

  

	 Combo    $eDP_VSwingPreEmph_5, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
	 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

	  
  Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"
  
  Link "DTD Timings Table" , "DTD Timings"
  Link "LFP PnP ID Table" , "LFP PnP ID"
  Link "Backlight Control Parameters" , "Backlight Control Parameters"
  Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

  #IF	0; $LVDS_Config == 3; Int eDP
    Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
  #ENDIF	; IVM OR IVD


  #IF	$LVDS_Config == 1 ; Int LVDS
    Combo	$Int_LVDS_Panel_5_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
    Help	"SETTINGS :\r\n"
    "Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
    "Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
    "Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Co        ntrol with respect to Channel Selection.\r\n"
    "Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
    "			   X >= 1280, Check Y-Resolution.\r\n"
    "Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
    "			  Y > 800, Set LVDS for Dual Channel.\r\n"
  #ENDIF	; $LVDS_Config == 1 ; Int LVDS


  #IF	$LVDS_Config == 1 
    Combo	$INT_Panel_Color_Depth05, "Panel Color Depth:", &Panel_Color_Depth_List,
    Help	"This feature specifies the color depth of the integrated LFP panel used. "
  #ENDIF	; $LVDS_Config == 1 


  #IF	$LVDS_Config == 3 ; eDP
    Combo	$eDP_Panel_Color_Depth_05, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
    Help	"This feature specifies the color depth of eDP panel used. "
  #ENDIF	; $LVDS_Config == 3 ; eDP

  

  #IF	$LVDS_Config == 1 ; Int LVDS
    Title	"Spread Spectrum Clock Features"
    Combo	$Enable_SSC05, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
    Help	"This feature when enabled will instruct software to use the "
    "external Spread Spectrum input clock as the internal LFP "
    "PLL reference clock.  Otherwise, when disabled, the internal "
    "reference clock will be used as the internal LFP PLL "
    "reference clock ignoring any Spread Spectrum input clock.\r\n"
    "\r\n"
    "Note: When enabling SSC option, please make sure that the hardware/"
    "system BIOS has enabled this feature in the chipset platform. "
    "The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
    "option must match the actual SSC frequency determined by platform "
    "hardware and/or system BIOS."
    "\r\n"
    "Note: This option is for internal LFP only.\r\n"
    "\r\n"
    "Note: Currently, this feature will also replace the CRT PLL "
    "reference clock on the same pipe that may cause CRT jitter.  "
    "Ideas to help this situation are to remove single pipe "
    "simultaneous display combinations (dual display twin) or use "
    "the 'Disable SSC in Dual Display Twin' option to "
    "automatically switch back to internal reference clock when "
    "entering a dual display twin display combination."
    Combo	$SSC_Freq05, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
    Help	"The SSC frequency selected must match the actual SSC frequency "
    "determined by platform hardware and/or system BIOS.\r\n"
    Combo	$Disable_SSC_DDT05, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
    Help	"This feature allows a selectable option for OEMs to disable "
    "Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
    "Pipe Simultaneous mode.\r\n"
    "\r\n"
    "Note: Disabling means that SSC will not be enabled while "
    "Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
    "when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

    Title	"eDP Spread Spectrum Clock Features"
    Combo	$Enable_SSC05, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
    Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

  #ENDIF	; $LVDS_Config == 1 ; Int LVDS


  #IF	$LVDS_Config == 3 ; eDP
    Combo	$edp_S3D_Feature_05, "  Steroscopic 3D:", &Disabled_Enabled_List,
    Help	"This feature allows a selectable option to determine whether "
    "to enable/disable S3D feature in driver.\r\n"
  #ENDIF	; $LVDS_Config == 3 ; eDP

  Title	"DPS Panel Type Features (Mobile only)"
  Combo	$DPS_Panel_Type_05, "  DPS Panel Type:", &DPS_Panel_Type_List,
  Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
  "Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
  "which reduces display Power\r\n"
  "SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
  "rate will not adversely impact the user experience\r\n"
  "Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
  "rate will not adversely impact the user experience.Implements seamless refresh\r\n"
  "rate switching, which eliminates the screen blink that occurred\r\n" 
  "during the refresh rate transitions\r\n"

  #IF	$Chipset >= 17 && $Chipset <= 18	; SNB

    #IF	$LVDS_Config == 3 ; eDP
      Combo	$eDP_sDRRS_MSA_Delay_05, "  MSA Timing Delay:", &MSA_TimingDelay_List,
      Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
      "The sDRRS timing switch shall occur on same line as the MSA\r\n"
      "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
      "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
      "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
      "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
    #ENDIF	; $LVDS_Config == 3 ; eDP

  #ENDIF	; SNB

  
  Title	"BackLight Technology Type Features (Mobile only)"
  Combo	$Blt_Control_05, "  BackLight Technology:", &Blt_Control_Type_List,
  Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile

      
      #IF	$Chipset >= 19		; IVB and above 
     	  #IF  $LVDS_Config == 3	; Int eDP
		  Title " "
                  Link "PSR feature" ,"PSR feature"
	  #ENDIF			; eDP
      #ENDIF				; IVB Mobile and above


#IF	$LVDS_Config == 1 ; Int LVDS
  Page "Panel Power Sequencing"
    
    Link	"Close Table" , ".."
    
    EditNum	$Power_On_Backlight_Enable_Delay_05, "  Power On to Backlight Enable Delay Time:", DEC,
    Help	"This feature specifies the panel Power sequencing time "
    "for delay of Power on to backlight enable."

    EditNum	$PowerUpDelay_05, "  Panel Power Up Delay Time:", DEC,
    Help	"This feature specifies the panel Power sequencing time "
    "for panel Power up delay. Note: This value "
    "is typically T1 + T2."

    EditNum	$Power_Backlight_Off_Power_Down_Delay_05, "  Power Backlight Off to Power Down Delay Time:", DEC,
    Help	"This feature specifies the panel Power sequencing time "
    "for Power backlight off to Power down delay."

    EditNum	$PowerDownDelay_05, "  Panel Power Down Delay Time:", DEC,
    Help	"This feature specifies the panel Power sequencing time "
    "for Power down delay."
    
    EditNum	$PowerCycleDelay_05, "  Panel Power Cycle Delay Time:", DEC,
    Help	"This feature specifies the panel Power sequencing time "
    "for Power Cycle delay."
    "\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
    "to have a delay of 400ms, programming value should be 5 instead of 4"
  EndPage
      #ELSEIF	$LVDS_Config == 3 ; eDP
  Page	"Panel Power Sequencing"
    Link	"Close Table", ".."
	
			Combo	$eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
  EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

  Link	"Close Table" , ".."

  Table	$DVO_Tbl_05 " DTD Timings Values",
  Column "Timings" , 1 byte , EHEX,
  Help	"This feature allows for the definition of the DTD "
  "timings parameters related to the LFP.  The "
  "table is the 18-byte DTD structure defined in the "
  "VESA EDID version 1.x.\r\n"  
  "\r\n"
  "\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
  "\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
  "\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
  "\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
  "\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
  "\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
  "\tByte6 \t: Vertical Active in lines, LSB\r\n"
  "\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
  "\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
  "\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
  "\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
  "\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
  "\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
  "\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
  "\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
  "\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
  "\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
  "\tByte13 \t: Horizontal Image Size, LSB\r\n"
  "\tByte14 \t: Vertical Image Size, LSB\r\n"
  "\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
  "\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
  "\tByte16 \t: Horizontal Border in pixels\r\n"
  "\tByte17 \t: Vertical Border in lines\r\n"
  "\tByte18 \t: Flags:\r\n"
  "\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
  "\t   \t:   Bit 6-5: 00 = Reserved\r\n"
  "\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
  "\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
  "\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
  "\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

  Link	"Close Table" , ".."

  Table	$LVDS_PnP_ID_05 " LFP PnP ID Values",
  Column "PnP ID" , 1 byte , EHEX,
  Help	"This feature allows the 10 bytes of EDID Vendor / "
  "Product ID starting at offset 08h to be used as a "
  "PnP ID.\r\n"
  "\r\n"
  " Table Definition:\r\n"
  "  Word:  ID Manufacturer Name\r\n"
  "  Word:  ID Product Code\r\n"
  "  DWord: ID Serial Number\r\n"
  "  Byte:  Week of Manufacture\r\n"
  "  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

  Link	"Close Table" , ".."

  Combo	$BLC_Inv_Type_5, "  Inverter Type:", &Inv_Type_List,
  Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

  Combo	$BLC_Inv_Polarity_5, "  Inverter Polarity:", &Inv_Polarity_List,
  Help	"This feature allows the backlight inverter polarity "
  "to be specified.\r\n"
  "\r\n"
  "Normal means 0 value is minimum brightness.\r\n"
  "Inverted means 0 value is maximum brightness."

  EditNum	$BLC_Min_Brightness_5, "  Minimum Brightness:", DEC,
  Help	"This feature allows defining the absolute minimum "
  "backlight brightness setting.  The graphics driver "
  "will never decrease the backlight less than this "
  "value.  The value must be specified using normal "
  "polarity semantics."

  EditNum	$POST_BL_Brightness_05, "  POST Brightness:", DEC,
  Help	"This feature is used only by video BIOS to set initial "
  "brightness level at POST. \r\n"
  "This is configurable field of 0-255. "
  "Value of 0 inidicates Zero brightness, 255 indicates maximum "
  "brightness."

  EditNum	$PWM_Frequency_5, "  PWM Inverter Frequency (Hz):", DEC,
  Help	"This feature allows for the definition of the "
  "frequency needed for PWM Inverter.\r\n"
  "\r\n"
  "Note: The frequency range, entered as a decimal "
  "number, for the integrated PWM is 200Hz - 40KHz."

      ;          Combo	$BLC_GPIO_Pins_5, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
      ;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
      ;          "this device."

      ;          Combo	$BLC_GMBus_Speed_5, "  I2C Bus Frequency:", &GMBus_Speed_List,
      ;          Help	"Selects the I2C bus frequency to use when "
      ;          "communicating to this device."

      ;          EditNum	$BLC_I2C_Addr_5, "  I2C Device Address:", HEX,
      ;          Help	"Selects the I2C device address for communication to "
      ;          "this backlight inverter.  The device address should "
      ;          "be in 8-bit format with the slave address assigned to "
      ;          "bits 7:1 and bit 0 cleared.  For example, the slave "
      ;          "address 0101100b would be stated here as 58h."

      ;          EditNum	$BLC_Brightness_Cmd_5, "  I2C Device, Display Brightness Command Code:", HEX,
      ;          Help	"Selects the command code (register index) for setting "
      ;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_5, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_5, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_5, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_5, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_5, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_5, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_5, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_5, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_5, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_5, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_5, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_5, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
  Page "eDP Fast Link Training Configuration Parameters"
    Link	"Close Table" , ".."
    
    Combo	$Fast_Link_Training_Supported_05, "  Is Fast Link Training feature supported:", &No_Yes_List,
          Help	"This feature allows for the selection of the "
          "Fast Link Training feature is to be enabled or disabled."
        
    Combo	$eDP_Link_DataRate_05, "  Data Rate:", &eDP_Link_DataRate_List,
    Help	"This feature allows for the selection of the "
    "Data Rate for the embedded DP link. It will be used if the "
    "sink indicates that no aux handshake is required during link training."

    Combo	$eDP_Link_LaneCount_05, "  Lane Count:", &eDP_Link_LaneCount_List,
    Help	"This feature allows for the selection of the "
    "Lane Count (Port Width) for the embedded DP link. It will be used if the "
    "sink indicates that no aux handshake is required during link training."

    Combo	$eDP_Link_PreEmp_05, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
   Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
      	Combo	$eDP_Link_VSwing_05, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
		
          
     EndPage
  
     #IF	$Chipset >= 19		; IVB and above 

          Page "PSR feature"
            Link	"Close Table" , ".."
			
            Combo	$PSR_FullLink_Enable_05, "Full Link enable:", &Yes_No_List,
            Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
            Combo	$PSR_Require_AUX2Wakeup_05, "Require AUX to wake up:", &Yes_No_List,
            Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		 
		
            Combo	$PSR_Lines2Wait_B4LinkS3_05, "Lines to wait before link standby:", &wait_line_link,
            Help	"This field determines Lines to wait before link standby \n"
                    "Note: This is applicable only on Haswell \n"

            EditNum	$PSR_IdleFrames2Wait_05, "Idle frames to wait:", DEC,
            Help	"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"

            EditNum	$PSR_TP1_WaitTime_05, "TP1 WakeUp Time:", DEC,
            Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
					"TP1 wake up time in multiples of 100us \n"
		
            EditNum	$PSR_TP_2_3_WaitTime_05, "TP2/TP3 WakeUp Time:", DEC,
            Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
					"TP2/TP3 wake up time in multiples of 100us"
        
	  EndPage		; PSR feature
       #ENDIF			; IVB Mobile and above
     #ENDIF			; $LVDS_Config == 3 ; eDP



#IF	0; $LVDS_Config == 3 ; eDP
  Page "Black Frame Insertion Parameters"
    Link	"Close Table" , ".."

    Combo	$BFI_Enable_05, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
    Help	"This feature allows the enabling of Black frame Insertion in Driver."

    Combo	$Brightness_Enable_05, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
    Help	"This feature allows the enabling of brightness adjustment in CUI."

    EditNum	$Brightness_non_BFI_05, " Brightness % in when BFI not enabled:", DEC,
    Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
  EndPage
#ENDIF	; eDP

EndPage
;==============================================================================
; Page - Panel #6 (1400x1050) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #6 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_06, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters  an  d rest of the characters will be truncated. "

EditNum	$Panel_Width_06, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_06, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_6, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
    "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"


Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
  Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD


#IF	$LVDS_Config == 1 ; Int LVDS
  Combo	$Int_LVDS_Panel_6_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
  Help	"SETTINGS :\r\n"
  "Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
  "Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
  "Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Co    nt  rol with respect to Channel Selection.\r\n"
  "Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
  "			   X >= 1280, Check Y-Resolution.\r\n"
  "Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
  "			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 1 
  Combo	$INT_Panel_Color_Depth06, "Panel Color Depth:", &Panel_Color_Depth_List,
  Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 


#IF	$LVDS_Config == 3 ; eDP
  Combo	$eDP_Panel_Color_Depth_06, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
  Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP



#IF	$LVDS_Config == 1 ; Int LVDS
  Title	"Spread Spectrum Clock Features"
  Combo	$Enable_SSC06, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
  Help	"This feature when enabled will instruct software to use the "
  "external Spread Spectrum input clock as the internal LFP "
  "PLL reference clock.  Otherwise, when disabled, the internal "
  "reference clock will be used as the internal LFP PLL "
  "reference clock ignoring any Spread Spectrum input clock.\r\n"
  "\r\n"
  "Note: When enabling SSC option, please make sure that the hardware/"
  "system BIOS has enabled this feature in the chipset platform. "
  "The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
  "option must match the actual SSC frequency determined by platform "
  "hardware and/or system BIOS."
  "\r\n"
  "Note: This option is for internal LFP only.\r\n"
  "\r\n"
  "Note: Currently, this feature will also replace the CRT PLL "
  "reference clock on the same pipe that may cause CRT jitter.  "
  "Ideas to help this situation are to remove single pipe "
  "simultaneous display combinations (dual display twin) or use "
  "the 'Disable SSC in Dual Display Twin' option to "
  "automatically switch back to internal reference clock when "
  "entering a dual display twin display combination."
  Combo	$SSC_Freq06, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
  Help	"The SSC frequency selected must match the actual SSC frequency "
  "determined by platform hardware and/or system BIOS.\r\n"
  Combo	$Disable_SSC_DDT06, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
  Help	"This feature allows a selectable option for OEMs to disable "
  "Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
  "Pipe Simultaneous mode.\r\n"
  "\r\n"
  "Note: Disabling means that SSC will not be enabled while "
  "Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
  "when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

  Title	"eDP Spread Spectrum Clock Features"
  Combo	$Enable_SSC06, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
  Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 3 ; eDP
  Combo	$edp_S3D_Feature_06, "  Steroscopic 3D:", &Disabled_Enabled_List,
  Help	"This feature allows a selectable option to determine whether "
  "to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_06, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB

  #IF	$LVDS_Config == 3 ; eDP
    Combo	$eDP_sDRRS_MSA_Delay_06, "  MSA Timing Delay:", &MSA_TimingDelay_List,
    Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
    "The sDRRS timing switch shall occur on same line as the MSA\r\n"
    "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
    "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
    "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
    "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
  #ENDIF	; $LVDS_Config == 3 ; eDP

#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_06, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile
     
#IF	$Chipset >= 19		; IVB and above 
   #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
   #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"
  
  Link	"Close Table" , ".."
  
  EditNum	$Power_On_Backlight_Enable_Delay_06, "  Power On to Backlight Enable Delay Time:", DEC,
  Help	"This feature specifies the panel Power sequencing time "
  "for delay of Power on to backlight enable."

  EditNum	$PowerUpDelay_06, "  Panel Power Up Delay Time:", DEC,
  Help	"This feature specifies the panel Power sequencing time "
  "for panel Power up delay. Note: This value "
  "is typically T1 + T2."

  EditNum	$Power_Backlight_Off_Power_Down_Delay_06, "  Power Backlight Off to Power Down Delay Time:", DEC,
  Help	"This feature specifies the panel Power sequencing time "
  "for Power backlight off to Power down delay."

  EditNum	$PowerDownDelay_06, "  Panel Power Down Delay Time:", DEC,
  Help	"This feature specifies the panel Power sequencing time "
  "for Power down delay."
  
  EditNum	$PowerCycleDelay_06, "  Panel Power Cycle Delay Time:", DEC,
  Help	"This feature specifies the panel Power sequencing time "
  "for Power Cycle delay."
  "\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
  "to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
  Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS


Page "DTD Timings"
Link	"Close Table" , ".."

Table	$DVO_Tbl_06 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_06 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_6, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_6, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_6, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_06, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_6, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

  ;          Combo	$BLC_GPIO_Pins_6, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
  ;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
  ;          "this device."

  ;          Combo	$BLC_GMBus_Speed_6, "  I2C Bus Frequency:", &GMBus_Speed_List,
  ;          Help	"Selects the I2C bus frequency to use when "
  ;          "communicating to this device."

  ;          EditNum	$BLC_I2C_Addr_6, "  I2C Device Address:", HEX,
  ;          Help	"Selects the I2C device address for communication to "
  ;          "this backlight inverter.  The device address should "
  ;          "be in 8-bit format with the slave address assigned to "
  ;          "bits 7:1 and bit 0 cleared.  For example, the slave "
  ;          "address 0101100b would be stated here as 58h."

  ;          EditNum	$BLC_Brightness_Cmd_6, "  I2C Device, Display Brightness Command Code:", HEX,
  ;          Help	"Selects the command code (register index) for setting "
  ;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_6, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_6, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_6, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_6, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_6, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_6, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_6, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_6, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_6, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_6, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_6, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_6, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

  Link	"Close Table" , ".."
  
  Combo	$Fast_Link_Training_Supported_06, "  Is Fast Link Training feature supported:", &No_Yes_List,
  Help	"This feature allows for the selection of the "
  "Fast Link Training feature is to be enabled or disabled."
        
  Combo	$eDP_Link_DataRate_06, "  Data Rate:", &eDP_Link_DataRate_List,
  Help	"This feature allows for the selection of the "
  "Data Rate for the embedded DP link. It will be used if the "
  "sink indicates that no aux handshake is required during link training."

  Combo	$eDP_Link_LaneCount_06, "  Lane Count:", &eDP_Link_LaneCount_List,
  Help	"This feature allows for the selection of the "
  "Lane Count (Port Width) for the embedded DP link. It will be used if the "
  "sink indicates that no aux handshake is required during link training."

  Combo	$eDP_Link_PreEmp_06, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
  Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
	Combo	$eDP_Link_VSwing_06, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
	
EndPage

#IF	$Chipset >= 19		; IVB and above 
  Page "PSR feature"
  Link	"Close Table" , ".."
			
  Combo	$PSR_FullLink_Enable_06, "Full Link enable:", &Yes_No_List,
  Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
  
  Combo	$PSR_Require_AUX2Wakeup_06, "Require AUX to wake up:", &Yes_No_List,
  Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		 
		
  Combo	$PSR_Lines2Wait_B4LinkS3_06, "Lines to wait before link standby:", &wait_line_link,
  Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

  EditNum	$PSR_IdleFrames2Wait_06, "Idle frames to wait:", DEC,
  Help	"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"

  EditNum	$PSR_TP1_WaitTime_06, "TP1 WakeUp Time:", DEC,
  Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
  EditNum	$PSR_TP_2_3_WaitTime_06, "TP2/TP3 WakeUp Time:", DEC,
  Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"
  Link	"Close Table" , ".."

  Combo	$BFI_Enable_06, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
  Help	"This feature allows the enabling of Black frame Insertion in Driver."

  Combo	$Brightness_Enable_06, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
  Help	"This feature allows the enabling of brightness adjustment in CUI."

  EditNum	$Brightness_non_BFI_06, " Brightness % in when BFI not enabled:", DEC,
  Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
;==============================================================================
; Page - Panel #7 (1600x1200) Flat Panel parameters
;------------------------------------------------------------------------------

Page "Panel #7 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_07, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_07, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_07, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_7, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD


#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_7_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth07, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 


#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_07, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP



#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC07, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq07, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT07, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC07, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_07, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_07, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB

#IF	$LVDS_Config == 3 ; eDP
  Combo	$eDP_sDRRS_MSA_Delay_07, "  MSA Timing Delay:", &MSA_TimingDelay_List,
  Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
  "The sDRRS timing switch shall occur on same line as the MSA\r\n"
  "Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
  "Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
  "Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
  "Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_07, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile
       
     
#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_07, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_07, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_07, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_07, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_07, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS


Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_07 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_07 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_7, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_7, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_7, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_07, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_7, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_7, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_7, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_7, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
"address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_5, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_7, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_7, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_7, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_7, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_7, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_7, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_7, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_7, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_7, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_7, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_7, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_7, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_07, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_07, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_07, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_07, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
 Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_07, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
		
	
          
EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_07, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_07, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		 
Combo	$PSR_Lines2Wait_B4LinkS3_07, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

EditNum	$PSR_IdleFrames2Wait_07, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
					"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_07, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_07, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_07, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_07, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_07, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #8 (1280x768) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #8 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_08, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_08, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_08, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_8, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"


Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD


#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_8_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth08, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 


#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_08, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP



#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC08, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq08, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT08, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC08, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_08, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_08, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_08, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_08, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile

#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above
	     
#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_08, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_08, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_08, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_08, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_08, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS


Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_08 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_08 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_8, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_8, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_8, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_08, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_8, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_8, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_8, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_8, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_8, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_8, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_8, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_8, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_8, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_8, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_8, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_8, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_8, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_8, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_8, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_8, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_8, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_08, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_08, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_08, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_08, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
  Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_08, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
		

EndPage


#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_08, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_08, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
Combo	$PSR_Lines2Wait_B4LinkS3_08, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

EditNum	$PSR_IdleFrames2Wait_08, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_08, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_08, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_08, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_08, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_08, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #9 (1680x1050) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #9 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_09, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_09, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_09, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_9, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"


Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD


#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_9_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth09, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 


#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_09, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC09, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq09, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT09, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC09, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS


#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_09, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_09, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_09, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_09, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile
       
#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above


#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_09, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_09, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_09, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_09, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_09, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."
			
			Combo	$eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_09 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_09 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_9, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."
Combo	$BLC_Inv_Polarity_9, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_9, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_09, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_9, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_9, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_9, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_9, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_9, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_9, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_9, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_9, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_9, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_9, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_9, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_9, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_9, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_9, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_9, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_9, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_9, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_09, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_09, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_09, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_09, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
 Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
			
		Combo	$eDP_Link_VSwing_09, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
		
EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_09, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_09, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		 
		
Combo	$PSR_Lines2Wait_B4LinkS3_09, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"
        
EditNum	$PSR_IdleFrames2Wait_09, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_09, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_09, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP

#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_09, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_09, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_09, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #10 (1920x1200) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #10 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_10, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_10, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_10, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_10, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
  Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
    "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"


Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD

#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_10_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth10, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 && $Chipset >= 15

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_10, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC10, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq10, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT10, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC10, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_10, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; SNB and above

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_10, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_10, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_10, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile

#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_10, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_10, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_10, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_10, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_10, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."
			Combo	$eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_10 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_10 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_10, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_10, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_10, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_10, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_10, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_10, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_10, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_10, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;         "be in 8-bit format with the slave address assigned to "
;         "bits 7:1 and bit 0 cleared.  For example, the slave "
;         "address 0101100b would be stated here as 58h."

;         EditNum	$BLC_Brightness_Cmd_10, "  I2C Device, Display Brightness Command Code:", HEX,
;         Help	"Selects the command code (register index) for setting "
;         "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_10, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_10, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_10, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_10, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_10, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_10, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_10, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_10, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_10, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_10, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_10, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_10, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_10, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_10, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_10, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_10, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
 Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_10, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
	
          
EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_10, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_10, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
Combo	$PSR_Lines2Wait_B4LinkS3_10, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

EditNum	$PSR_IdleFrames2Wait_10, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_10, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_10, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_10, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_10, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_10, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #11 (Reserved) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #11 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_11, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_11, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_11, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_11, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"


Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD

#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_11_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth11, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 



#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_11, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC11, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq11, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT11, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC11, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_11, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_11, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_11, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_11, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile

#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"
Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_11, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_11, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_11, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_11, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_11, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_11 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_11 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_11, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."
Combo	$BLC_Inv_Polarity_11, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_11, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_11, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_11, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_11, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_11, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_11, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_11, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_11, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_11, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_11, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_11, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_11, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_11, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_11, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_11, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_11, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_11, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_11, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_11, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_11, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_11, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_11, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_11, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
  Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_11, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
	      
EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_11, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_11, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
Combo	$PSR_Lines2Wait_B4LinkS3_11, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

EditNum	$PSR_IdleFrames2Wait_11, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable.\n "
		"Allowed values 0-15.Default value is 0. \n"
		
EditNum	$PSR_TP1_WaitTime_11, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_11, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_11, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_11, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_11, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #12 (Reserved) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #12 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_12, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_12, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_12, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_12, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD

#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_12_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth12, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_12, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC12, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq12, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT12, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC12, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_12, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; SNB and above

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_12, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_12, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_12, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile

#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_12, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_12, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_12, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_12, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_12, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_12 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_12 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_12, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."
Combo	$BLC_Inv_Polarity_12, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_12, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_12, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_12, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_12, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_12, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_12, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_12, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_12, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_12, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_12, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_12, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_12, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_12, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_12, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_12, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_12, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_12, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_12, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_12, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_12, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_12, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_12, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_12, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
  Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"

		Combo	$eDP_Link_VSwing_12, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
	      
EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_12, "  Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
	
Combo	$PSR_Require_AUX2Wakeup_12, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
Combo	$PSR_Lines2Wait_B4LinkS3_12, " Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

EditNum	$PSR_IdleFrames2Wait_12, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"
		
EditNum	$PSR_TP1_WaitTime_12, "  TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_12, "  TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP

#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_12, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_12, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_12, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #13 (Reserved) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #13 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_13, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_13, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_13, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."

 Combo    $eDP_VSwingPreEmph_13, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
  Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD

#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_13_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth13, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_13, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC13, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq13, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT13, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC13, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_13, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_13, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_13, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_13, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile


#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above


#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_13, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_13, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_13, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_13, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_13, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; Int LVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_13 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_13 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_13, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_13, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_13, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_13, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_13, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_13, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_13, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_13, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_13, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_13, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_13, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_13, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_13, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_13, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_13, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_13, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_13, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_13, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_13, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_13, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_13, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control
#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_13, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_13, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_13, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_13, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
  Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_13, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"      

EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_13, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_13, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
Combo	$PSR_Lines2Wait_B4LinkS3_13, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"
        
EditNum	$PSR_IdleFrames2Wait_13, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"
		
EditNum	$PSR_TP1_WaitTime_13, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_13, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"

EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_13, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_13, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_13, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #14 (1280x800) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #14 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_14, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_14, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_14, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_14, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
  Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD



#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_14_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth14, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_14, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC14, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq14, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT14, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC14, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_14, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP



Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_14, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_14, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features"
Combo	$Blt_Control_14, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile

#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_14, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_14, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_14, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_14, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_14, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_14 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_14 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_14, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_14, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_14, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_14, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_14, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_14, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_14, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_14, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_14, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_14, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_14, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_14, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_14, "   Blue_White_bits (Bits 1&0 at 20h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_14, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_14, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_14, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_14, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_14, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_14, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_14, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_14, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_14, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_14, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_14, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_14, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
 Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"
         
		Combo	$eDP_Link_VSwing_14, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"

EndPage


#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_14, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"

Combo	$PSR_Require_AUX2Wakeup_14, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
Combo	$PSR_Lines2Wait_B4LinkS3_14, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"

EditNum	$PSR_IdleFrames2Wait_14, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_14, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
	
EditNum	$PSR_TP_2_3_WaitTime_14, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"
EndPage		; PSR feature
#ENDIF		; IVB Mobile and above 
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0 ;$LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_14, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_14, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_14, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #15 (1280x600) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #15 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_15, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "

EditNum	$Panel_Width_15, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_15, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_15, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
 Help   "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
      "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"

Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD

#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_15_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth15, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_15, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP




#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC15, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq15, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT15, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC15, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_15, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP



Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_15, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_15, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_15, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile
        
#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above
	

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_15, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_15, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_15, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_15, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_15, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_15 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9 \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_15 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_15, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_15, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_15, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_15, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_15, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_15, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_15, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_15, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_15, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_15, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_15, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_15, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_15, "   Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_15, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_15, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_15, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_15, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_15, "   Blue_x (Bits 9->2 at 1Fh)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_15, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_15, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_15, "   White_y (Bits 9->2 at 22h)" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_15, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
    
Combo	$eDP_Link_DataRate_15, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_15, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_15, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
 Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis  table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"

		Combo	$eDP_Link_VSwing_15, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"      

EndPage

#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."
			
Combo	$PSR_FullLink_Enable_15, "Full Link enable:", &Yes_No_List,
Help	"If 'Full Link Enable' set to Yes, then Link is kept in standby state when the panel is in PSR\n"
		
Combo	$PSR_Require_AUX2Wakeup_15, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
				
Combo	$PSR_Lines2Wait_B4LinkS3_15, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"
        
EditNum	$PSR_IdleFrames2Wait_15, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_15, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_15, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"
EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_15, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_15, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_15, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage
      ;==============================================================================
      ; Page - Panel #16 (Reserved) Flat Panel parameters
      ;------------------------------------------------------------------------------

Page "Panel #16 "

Title	"Local Flat Panel (LFP) Size"


EditText   $Panel_Name_16, "LFP panel name:", 
Help	"This feature defines the LFP panel name, used by driver only. Panel name can be only of maximum 13 characters and rest of the characters will be truncated. "


EditNum	$Panel_Width_16, "LFP Width:", DEC,
Help	"This value specifies the LFP pixel width for this panel "
"type."

EditNum	$Panel_Height_16, "LFP Height:", DEC,
Help	"This value specifies the LFP pixel height (number of scan "
"lines) for this panel type."


 Combo    $eDP_VSwingPreEmph_16, "Select VSwing/Pre-Emphasis table :", &eDP_VSwing_Preemph_table_List,
  Help    "This feature selects the VSwing Pre-Emphasis setting table to be used. "
      "For Broadwell, based on the selection respective table will be used.\r\n"
     "Tables for Broadwell:-\r\n"
     "------------------------------------------------------------------------------------------------------\n"
     "|Low Power VSwing Pre-Emphasis Setting Table                                                        |\n"         
     "-----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                             |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0      | Level1/3.5      | Level2/6       | Level3/9.5           |\n"
     "| Voltage |-----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 200mV,0db  | 200mV,1.5db | 200mV,5db  |  200mV,9.5db     |\n"
     "| (mV)     |-----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 250mV,0db  | 250mV,3db    | 250mV,6db  |  NA                     |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 350mV,0db  | 350mV,3db    | NA               | NA                      |\n"
     "|              |-----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200  | NA              | NA                  | NA               | NA                      |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
     
     "-----------------------------------------------------------------------------------------------------\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "----------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0        | Level1/3.5        | Level2/6        | Level3/9.5    |\n"
     "| Voltage |---------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db    | 400mV,3.5db  | 400mV,6db    |  400mV,8db |\n"
     "| (mV)     |---------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db    | 600mV,3.5db  | 600mV,4.5db |  NA               |\n"
     "|              |---------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 850mV,0.5db | 750mV,2.5db  | NA                 | NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                 | NA                  | NA                 | NA                 |\n"
     "-----------------------------------------------------------------------------------------------------\n\n"
      
     "In case of Haswell irrespective of the table selection following table will be used.\r\n"
     "Table for Haswell:-\r\n"
     "---------------------------------------------------------------------------------------------------|\n"
     "|Default VSwing Pre-Emphasis Setting Table                                                              |\n"         
     "---------------------------------------------------------------------------------------------------|\n"
     "|              |                            Pre-Emphasis (db)                                                            |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | DP Applet     | Level0/0       | Level1/3.5        | Level2/6        | Level3/9.5     |\n"
     "| Voltage |----------------------------------------------------------------------------------------|\n"
     "| Swing   | Level0/400   | 400mV,0db   | 400mV,3.5db  | 400mV,6db    |  400mV,8dB  |\n"
     "| (mV)     |----------------------------------------------------------------------------------------|\n"
     "|              | Level1/600   | 600mV,0db   | 600mV,3.5db  | 600mV,4.5db |  NA                |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level2/800   | 800mV,0db   | 800mV,2db      | NA                 | NA                 |\n"
     "|              |----------------------------------------------------------------------------------------|\n"
     "|              | Level3/1200 | NA                | NA                   | NA                 | NA                 |\n"
     "----------------------------------------------------------------------------------------------------\n\n"


Link "Panel Power Sequencing Parameters Table" , "Panel Power Sequencing"

Link "DTD Timings Table" , "DTD Timings"
Link "LFP PnP ID Table" , "LFP PnP ID"
Link "Backlight Control Parameters" , "Backlight Control Parameters"
Link "eDP Fast Link Training Configuration Parameters" , "eDP Fast Link Training Configuration Parameters"
	    Link "Chromaticity Control" , "Chromaticity Control"

#IF	0; $LVDS_Config == 3; Int eDP
Link "Black Frame Insertion Parameters", "Black Frame Insertion Parameters"
#ENDIF	; IVM OR IVD

#IF	$LVDS_Config == 1 ; Int LVDS
Combo	$Int_LVDS_Panel_16_Channel_Type, "Integrated LFP Channel Type:", &INT_LVDS_Channel_List,
Help	"SETTINGS :\r\n"
"Single Channel : this option will initialize the Integrated LFP Port Control for Single Channel.\r\n"
"Dual Channel : this option will initialize the Integrated LFP Port Control for Dual Channel.\r\n"
"Automatic Selection : this option will implement the following algorithm for initializing the Integrated LFP Port Control with respect to Channel Selection.\r\n"
"Compare X-Resolution to 1280: X < 1280, Set LVDS for Single Channel.\r\n"
"			   X >= 1280, Check Y-Resolution.\r\n"
"Compare Y-Resolution to 800: Y <= 800, Set LVDS for Single Channel.\r\n"
"			  Y > 800, Set LVDS for Dual Channel.\r\n"
#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 1 
Combo	$INT_Panel_Color_Depth16, "Panel Color Depth:", &Panel_Color_Depth_List,
Help	"This feature specifies the color depth of the integrated LFP panel used. "
#ENDIF	; $LVDS_Config == 1 

#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_Panel_Color_Depth_16, "Panel Color Depth:", &eDP_Panel_Color_Depth_List,
Help	"This feature specifies the color depth of eDP panel used. "
#ENDIF	; $LVDS_Config == 3 ; eDP


#IF	$LVDS_Config == 1 ; Int LVDS
Title	"Spread Spectrum Clock Features"
Combo	$Enable_SSC16, "  LFP Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature when enabled will instruct software to use the "
"external Spread Spectrum input clock as the internal LFP "
"PLL reference clock.  Otherwise, when disabled, the internal "
"reference clock will be used as the internal LFP PLL "
"reference clock ignoring any Spread Spectrum input clock.\r\n"
"\r\n"
"Note: When enabling SSC option, please make sure that the hardware/"
"system BIOS has enabled this feature in the chipset platform. "
"The SSC frequency selected in 'LFP Spread Spectrum Clock Frequency' "
"option must match the actual SSC frequency determined by platform "
"hardware and/or system BIOS."
"\r\n"
"Note: This option is for internal LFP only.\r\n"
"\r\n"
"Note: Currently, this feature will also replace the CRT PLL "
"reference clock on the same pipe that may cause CRT jitter.  "
"Ideas to help this situation are to remove single pipe "
"simultaneous display combinations (dual display twin) or use "
"the 'Disable SSC in Dual Display Twin' option to "
"automatically switch back to internal reference clock when "
"entering a dual display twin display combination."
Combo	$SSC_Freq16, "  LFP Spread Spectrum Clock Frequency:", &SSC_List,
Help	"The SSC frequency selected must match the actual SSC frequency "
"determined by platform hardware and/or system BIOS.\r\n"
Combo	$Disable_SSC_DDT16, "  Disable SSC in Dual Display Twin:", &No_Yes_List,
Help	"This feature allows a selectable option for OEMs to disable "
"Spread Spectrum Clock in Dual Display Twin mode, i.e. Single "
"Pipe Simultaneous mode.\r\n"
"\r\n"
"Note: Disabling means that SSC will not be enabled while "
"Intel® Dual Twin (DDT) is running, SSC will be re-enabled "
"when DDT is exited."
#ELSEIF	$LVDS_Config == 3 ; eDP

 Title	"eDP Spread Spectrum Clock Features"
 Combo	$Enable_SSC16, "  eDP Spread Spectrum Clock:", &Disabled_Enabled_List,
 Help	"This feature will allow users to disable/enable Spread Spectrum Clock for eDP.\r\n "

#ENDIF	; $LVDS_Config == 1 ; Int LVDS

#IF	$LVDS_Config == 3 ; eDP
Combo	$edp_S3D_Feature_16, "  Steroscopic 3D:", &Disabled_Enabled_List,
Help	"This feature allows a selectable option to determine whether "
"to enable/disable S3D feature in driver.\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP

Title	"DPS Panel Type Features (Mobile only)"
Combo	$DPS_Panel_Type_16, "  DPS Panel Type:", &DPS_Panel_Type_List,
Help     "This feature allows OEM to select the DPS Panel Type.\r\n "
"Intel SDRRS Technology is a feature of the Intel graphics driver\r\n"
"which reduces display Power\r\n"
"SDRRS:- Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience\r\n"
"Seamless:-  Allows Power savings when on battery mode and when a lower refresh\r\n"
"rate will not adversely impact the user experience.Implements seamless refresh\r\n"
"rate switching, which eliminates the screen blink that occurred\r\n" 
"during the refresh rate transitions\r\n"

#IF	$Chipset >= 17 && $Chipset <= 18	; SNB
#IF	$LVDS_Config == 3 ; eDP
Combo	$eDP_sDRRS_MSA_Delay_16, "  MSA Timing Delay:", &MSA_TimingDelay_List,
Help     "It is intended for use with embedded DisplayPort panels that support sDRRS.\r\n "
"The sDRRS timing switch shall occur on same line as the MSA\r\n"
"Line 1: MSA and sDRRS timing switch occur within the first  line of vertical blank\r\n"
"Line 2: MSA and sDRRS timing switch occur within the second line of vertical blank\r\n"
"Line 3: MSA and sDRRS timing switch occur within the third  line of vertical blank\r\n"
"Line 4: MSA and sDRRS timing switch occur within the fourth line of vertical blank\r\n"
#ENDIF	; $LVDS_Config == 3 ; eDP
#ENDIF	; SNB


Title	"BackLight Technology Type Features (Mobile only)"
Combo	$Blt_Control_16, "  BackLight Technology:", &Blt_Control_Type_List,
Help     "This feature allows OEM to select the Backlight Technology.\r\n "
#ENDIF    ; Mobile
      
#IF	$Chipset >= 19		; IVB and above 
  #IF  $LVDS_Config == 3	; Int eDP
	  Title " "
          Link "PSR feature" ,"PSR feature"
  #ENDIF			; eDP
#ENDIF				; IVB Mobile and above

#IF	$LVDS_Config == 1 ; Int LVDS
Page "Panel Power Sequencing"

Link	"Close Table" , ".."

EditNum	$Power_On_Backlight_Enable_Delay_16, "  Power On to Backlight Enable Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for delay of Power on to backlight enable."

EditNum	$PowerUpDelay_16, "  Panel Power Up Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for panel Power up delay. Note: This value "
"is typically T1 + T2."

EditNum	$Power_Backlight_Off_Power_Down_Delay_16, "  Power Backlight Off to Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power backlight off to Power down delay."

EditNum	$PowerDownDelay_16, "  Panel Power Down Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power down delay."

EditNum	$PowerCycleDelay_16, "  Panel Power Cycle Delay Time:", DEC,
Help	"This feature specifies the panel Power sequencing time "
"for Power Cycle delay."
"\r\nNote:  The Panel Power Cycle Delay value to be programmed with '+1'. For instance, "
"to have a delay of 400ms, programming value should be 5 instead of 4"
EndPage
#ELSEIF	$LVDS_Config == 3 ; eDP
Page	"Panel Power Sequencing"
Link	"Close Table", ".."

			Combo	$eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List,
			Help	"This feature enables or disables T3 optimization. \r\n"
					"When enabled, software will poll for AUX soon after VDD enable until AUX passes or T3 time is reached\r\n"
					"When disabled, software will wait for T3 time before trying the first AUX transaction"

			EditNum    $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", DEC,
			Help       "Using this field the delay from LCDVCC to HPD high can be specified in 100uS.\r\n"
					   "Valid Range: 0 to 200msec\r\n"

			EditNum     $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Backlight Enable delay (T8):", DEC,
			Help        "Using this field the delay from Start of Valid video data from Source to Backlight Enable can be specified in 100uS.\r\n"
						"T8 is inclusive of T7.\r\n"
						"Valid Range of T7: 0 to 50msec\r\n"

			EditNum    $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enable delay:", DEC,
			Help       "Using this field the delay from PWM-On to Backlight Enable can be specified in 100uS.\r\n"
						"Delay from PWM-On to Backlight Enable is included in delay from Valid video data to Backlight Enable (T8).\r\n"
						"So it is expected that delay from PWM-On to Backlight Enable is less than the delay from Valid video data to Backlight Enable (T8).\r\n"

			EditNum    $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to PWM-Off delay:", DEC,
			Help       "Using this field delay from Backlight Disable to PWM-Off can be specified in 100uS.\r\n"
					   "Delay from Backlight Disable to PWM-Off is included in delay from Backlight Disable to End of Valid video data (T9).\r\n"
					   "So it is expected that delay from Backlight Disable to PWM-Off delay is less than the delay from Backlight Disable to to End of Valid video data (T9).\r\n"
		
			EditNum    $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to End of Valid video data delay (T9):", DEC,
			Help       "Using this field the delay from Backlight Disable to End of Valid video data can be specified in 100uS.\r\n"
					
			EditNum    $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data to Power-Off delay (T10):", DEC,
			Help       "Using this field delay from End of Valid video data from Source to Power-Off can be specified in 100uS.\r\n"
						"Valid Range: 0 to 500 msec\r\n"

	        EditNum    $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC,
	        Help       "Using this field Power-off time can be specified in 100uS.\r\n"
EndPage
#ENDIF	; $LVDS_Config == 1 ; iLVDS



Page "DTD Timings"

Link	"Close Table" , ".."

Table	$DVO_Tbl_16 " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"port timings parameters related to the LFP.  The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage

Page "LFP PnP ID"

Link	"Close Table" , ".."

Table	$LVDS_PnP_ID_16 " LFP PnP ID Values",
Column "PnP ID" , 1 byte , EHEX,
Help	"This feature allows the 10 bytes of EDID Vendor / "
"Product ID starting at offset 08h to be used as a "
"PnP ID.\r\n"
"\r\n"
" Table Definition:\r\n"
"  Word:  ID Manufacturer Name\r\n"
"  Word:  ID Product Code\r\n"
"  DWord: ID Serial Number\r\n"
"  Byte:  Week of Manufacture\r\n"
"  Byte:  Year of Manufacture"
EndPage

Page "Backlight Control Parameters"

Link	"Close Table" , ".."

Combo	$BLC_Inv_Type_16, "  Inverter Type:", &Inv_Type_List,
Help	"This feature selects the "
        "Backlight Inverter type that is used to "
        "control backlight brightness of LFP.  When "
        "PWM is selected, the driver and GOP/VBIOS control "
        "the backlight brightness via integrated PWM "
        "solution for the chipsets.  When None/External is "
        "selected, the system BIOS controls the backlight "
        "brightness via external solution."

Combo	$BLC_Inv_Polarity_16, "  Inverter Polarity:", &Inv_Polarity_List,
Help	"This feature allows the backlight inverter polarity "
"to be specified.\r\n"
"\r\n"
"Normal means 0 value is minimum brightness.\r\n"
"Inverted means 0 value is maximum brightness."

EditNum	$BLC_Min_Brightness_16, "  Minimum Brightness:", DEC,
Help	"This feature allows defining the absolute minimum "
"backlight brightness setting.  The graphics driver "
"will never decrease the backlight less than this "
"value.  The value must be specified using normal "
"polarity semantics."

EditNum	$POST_BL_Brightness_16, "  POST Brightness:", DEC,
Help	"This feature is used only by video BIOS to set initial "
"brightness level at POST. \r\n"
"This is configurable field of 0-255. "
"Value of 0 inidicates Zero brightness, 255 indicates maximum "
"brightness."

EditNum	$PWM_Frequency_16, "  PWM Inverter Frequency (Hz):", DEC,
Help	"This feature allows for the definition of the "
"frequency needed for PWM Inverter.\r\n"
"\r\n"
"Note: The frequency range, entered as a decimal "
"number, for the integrated PWM is 200Hz - 40KHz."

;          Combo	$BLC_GPIO_Pins_16, "  I2C Bus GPIO Pin Pair:", &GPIO_Pin_List,
;          Help	"Selects the GPIO pin pair to use as the I2C bus for "
;          "this device."

;          Combo	$BLC_GMBus_Speed_16, "  I2C Bus Frequency:", &GMBus_Speed_List,
;          Help	"Selects the I2C bus frequency to use when "
;          "communicating to this device."

;          EditNum	$BLC_I2C_Addr_16, "  I2C Device Address:", HEX,
;          Help	"Selects the I2C device address for communication to "
;          "this backlight inverter.  The device address should "
;          "be in 8-bit format with the slave address assigned to "
;          "bits 7:1 and bit 0 cleared.  For example, the slave "
;          "address 0101100b would be stated here as 58h."

;          EditNum	$BLC_Brightness_Cmd_16, "  I2C Device, Display Brightness Command Code:", HEX,
;          Help	"Selects the command code (register index) for setting "
;          "the backlight brightness."
EndPage

	    Page	"Chromaticity Control"
	    	Link	"Close Table" , ".."

			Combo	$Chromacity_Enable_16, "Chromaticity Control Feature", &Disabled_Enabled_List,
			Help	" This bit enables Chromaticity feature. \r\n"
					" If this bit is enabled, EDID values for chromaticity will be used, else feature is disabled. \r\n"
					" Feature will be supported for Panels that support EDID version 1.4 or higher. \r\n"
					" Please refer to section 3.7 of EDID Specification 1.4"
			Combo	$Override_EDID_Data_16, "Override the EDID values", &No_Yes_List,
			Help	"This option when enabled along with Chromaticity feature will override EDID values through following VBT data"
	    	EditNum	$Red_Green_16, "   Red_Green_bits (Bits 1&0 at 19h)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Red, Green Coordinates represented as Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0" 
	    	EditNum	$Blue_White_16, "   Blue_White_bits (Bits 1&0 at 1Ah)" , EHEX,
	    	Help	" Lower order bytes (bits 1 and 0) of Blue, White Coordinates represented as Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0"
	    	EditNum	$Red_x_16, "   Red_x (Bits 9->2 at 1Bh)" , EHEX,
	    	Help	" Bits 9->2 of red color x coordinate"
	    	EditNum	$Red_y_16, "   Red_y (Bits 9->2 at 1Ch)" , EHEX,
	    	Help	" Bits 9->2 of red color y coordinate"
		    EditNum	$Green_x_16, "   Green_x (Bits 9->2 at 1Dh)" , EHEX,
	    	Help	" Bits 9->2 of Green color x coordinate"
		    EditNum	$Green_y_16, "   Green_y (Bits 9->2 at 1Eh)" , EHEX,
	    	Help	" Bits 9->2 of Green color y coordinate"
		    EditNum	$Blue_x_16, "   Blue_x (Bits 9->2 at 1F)" , EHEX,
	    	Help	" Bits 9->2 of Blue color x coordinate"
		    EditNum	$Blue_y_16, "   Blue_y (Bits 9->2 at 20h)" , EHEX,
	    	Help	" Bits 9->2 of Blue color y coordinate"
		    EditNum	$White_x_16, "   White_x (Bits 9->2 at 21h)" , EHEX,
	    	Help	" Bits 9->2 of White color x coordinate"
		    EditNum	$White_y_16, "   White_y (Bits 9->2 at 22h)h" , EHEX,
	    	Help	" Bits 9->2 of White color y coordinate"

	  	EndPage	; Chromaticity Control

#IF	$LVDS_Config == 3 ; eDP
Page "eDP Fast Link Training Configuration Parameters"

Link	"Close Table" , ".."

Combo	$Fast_Link_Training_Supported_16, "  Is Fast Link Training feature supported:", &No_Yes_List,
Help	"This feature allows for the selection of the "
"Fast Link Training feature is to be enabled or disabled."
        
Combo	$eDP_Link_DataRate_16, "  Data Rate:", &eDP_Link_DataRate_List,
Help	"This feature allows for the selection of the "
"Data Rate for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_LaneCount_16, "  Lane Count:", &eDP_Link_LaneCount_List,
Help	"This feature allows for the selection of the "
"Lane Count (Port Width) for the embedded DP link. It will be used if the "
"sink indicates that no aux handshake is required during link training."

Combo	$eDP_Link_PreEmp_16, "  Pre-Emphasis :", &DP_Link_PreEmp_List,
 Help	"This feature allows for the selection of the "
          "Pre-Emphasis value for the embedded DP link. It will be used if the "
          "sink indicates that no aux handshake is required during link training. \n\n"
          "In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
          "In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
		  "Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
		  "For Example: Panel #3 is configured for eDP.Under Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
		  " either default or Low Power VSwing/Pre-Emphasis table given in help text. \n"

		Combo	$eDP_Link_VSwing_16, "  Voltage Swing:", &DP_EDP_Link_VSwing_List,
		Help	"This feature allows for the selection of the "
				"Voltage Swing value for the embedded DP link. It will be used if the "
				"sink indicates that no aux handshake is required during link training.\n\n"
				"In case of Haswell, for Level-0,Level-1,Level-2 and Level-3 definitions, please refer to DP spec.\n\n"
				"In case of Broadwell, for Level-0,Level-1,Level-2 and Level-3 definitions \n"
				"Please refer to help text of 'Select VSwing/Pre-Emphasis table' which is displayed under each Panel configuration Page(example Panel #1,Panel #2....Panel #16) \n\n"
				"For Example: Panel #3 is configured for eDP.On Panel #3 page, select either default or Low Power VSwing/Pre-Emphasis table option in 'Select VSwing/Pre-Emphasis table'.Based on selection refer to"
				" either default or Low Power VSwing/Pre-Emphasis table given in help text. \n\n"
				"Note: Level3 is not listed in drop down list because Broadwell and Haswell does not support\n"
          
EndPage


#IF	$Chipset >= 19		; IVB and above 
Page "PSR feature"
Link	"Close Table" , ".."

Combo	$PSR_FullLink_Enable_16, "Full Link enable:", &Yes_No_List,
Help	"When panel is in PSR mode and 'Full Link Enable' is set to Yes, Link is kept in standby state.\n"
		
Combo	$PSR_Require_AUX2Wakeup_16, "Require AUX to wake up:", &Yes_No_List,
Help	"When panel is exiting PSR mode and 'Require AUX to wake up' is set to Yes, the AUX channel handshake(link training is required) will be used.\n"
		
		
Combo	$PSR_Lines2Wait_B4LinkS3_16, "Lines to wait before link standby:", &wait_line_link,
Help	"This field determines Lines to wait before link standby \n"
        "Note: This is applicable only on Haswell \n"
        
EditNum	$PSR_IdleFrames2Wait_16, "Idle frames to wait:", DEC,
Help	"Idle frames to wait for PSR enable. \n "
		"Allowed values 0-15.Default value is 0. \n"

EditNum	$PSR_TP1_WaitTime_16, "TP1 WakeUp Time:", DEC,
Help	"This field selects the link training TP1(Training Pattern1) time during PSR exit(wake up)\n"
		"TP1 wake up time in multiples of 100us \n"
		
EditNum	$PSR_TP_2_3_WaitTime_16, "TP2/TP3 WakeUp Time:", DEC,
Help	"This field selects the link training TP2(Training Pattern2) or TP3(Training Pattern3) time during PSR exit(wake up)\n"
		"TP2/TP3 wake up time in multiples of 100us"
EndPage		; PSR feature
#ENDIF		; IVB Mobile and above
#ENDIF		; $LVDS_Config == 3 ; eDP


#IF	0; $LVDS_Config == 3 ; eDP
Page "Black Frame Insertion Parameters"

Link	"Close Table" , ".."

Combo	$BFI_Enable_16, " Black Frame Insertion Feature:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of Black frame Insertion in Driver."

Combo	$Brightness_Enable_16, " Enable Brightness Adjustment in CUI:", &Disabled_Enabled_List,
Help	"This feature allows the enabling of brightness adjustment in CUI."

EditNum	$Brightness_non_BFI_16, " Brightness % in when BFI not enabled:", DEC,
Help	"This values give % brightness of BLC when BFI is enabled, but currently off."
EndPage
#ENDIF	; eDP

EndPage	; "Panel #16 "
;    EndPage ; "Integrated LFP Features"
#ENDIF	; ($LVDS_Config == 1) || ($LVDS_Config == 3) ; Int LVDS or eDP
EndPage

;==============================================================================
; Page - Integrated DisplayPort/HDMI Configuration
;------------------------------------------------------------------------------

Page "Integrated DisplayPort/HDMI Configuration with External Connectors"
Title	"Configurations for DisplayPort/HDMI Solution (External Connectors):"
Link	"Close Window" , ".."

Title "DisplayPort SSC configuration: " 
Combo	$DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum Clock:", &Disabled_Enabled_List,
Help	"This feature allow OEMs to enable/disable SSC for external DisplayPort.  "
"This feature is valid only the attached DisplayPort panel support SSC "
"\r\n"

Combo	$DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/Disable for Dongles:", &Disabled_Enabled_List,
Help "This feature is to enable or disable DisplayPort Dongle Spread Spectrum Clock when dongle are used "
"and the attached DisplayPort panel should support SSC\r\n"

Title "DisplayPort Device Configuration " 
Link "Device 1 Configuration" , "Device 1 (EFP1)"
Link "Device 2 Configuration" , "Device 2 (EFP2)"
Link "Device 3 Configuration" , "Device 3 (EFP3)"

Page "Device 1 (EFP1)"

Link	"Close Window" , ".."

Combo	$Int_EFP1_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
;Combo   $Int_EFP1_Type_Compat, "Select Device Type:", &Int_EFP_Device_Type_List,
Help	"This feature specifies the Device Type for this "
"add-in device."

Combo	$Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List,
Help	"This feature specifies which DVO port the device is "

Combo	$Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
Help	"This feature specifies the GPIO pin pair "
"used as DDC bus by this device.  If this device "
"doesn't support DDC bus, this field will be ignored."

Combo	$Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
Help	"This feature specifies the AUX Channel for int-DisplayPort. "
"This field is valid only if integrated DP is selected for Device Type."


 Combo	$Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_Haswell_Broadwell_LS_List,
 Help	"This feature specifies the Level shifter configuration for HDMI. "
 "This field is valid only if HDMI is selected for Device Type.\r"
 "The values applicable to Broadwell/Haswell are mentioned in the braces."
 "Select value corresponding to the platform."

#IF	($Embedded_Platform == 1)	; Embedded platform
Title	"	"

Combo	$EFP1_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
Help	"If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."

Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
#ENDIF	;  Embedded platform

Title	"	"

Combo	$EFP1_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
Help	"This feature, when enabled, will set lane reversal bit for selected Port "


Combo	$Int_EFP1_Port_Dockable, "Dockable", &No_Yes_List,
Help	"This feature will describe if this port is dockable or not."	
Title "Select DisplayPort Redriver "
Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration"

Page	"DisplayPort Redriver Configuration"


Combo	$Int_EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List,
Help	"This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."

Combo	$Int_EFP1_OnBoard_Pre_emphasis, "  Pre-Emphasis Level:", &DP_Link_PreEmp_List,
Help	"This feature allows for the selection of "
"Pre-Emphasis level for the OnBoard redriver DP link.\n"
 "Level 0 (0 dB)\n"
 "Level 1 (3.5 dB)\n"
 "Level 2 (6.0 dB)\n"
 "Level 3 (9.5 dB)"

Combo	$Int_EFP1_OnBoard_Voltage_Swing, "  Voltage Swing Level:", &DP_EDP_Link_VSwing_List,
Help	"This feature allows for the selection of "
"Voltage Swing level for the OnBoard Redriver DP link.\n"
		  "Swing-0 (0.4 V)\n" 
		  "Swing-1 (0.6 V)\n"
		  "Swing-2 (0.8 V)\n" 


Title	"	"

Combo	$Int_EFP1_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
Help	"This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"
"Note: 5F14,078F GetMiscStatus system hook must be implemented in SBIOS and enabled in VBIOS "
"for this feature to work."

Combo	$Int_EFP1_Dock_Pre_emphasis, "  Pre-Emphasis Level:", &DP_Link_PreEmp_List,
Help	"This feature allows for the selection of "
"Pre-Emphasis level for the Dock redriver DP link."

Combo	$Int_EFP1_Dock_Voltage_Swing, "  Voltage Swing Level:", &DP_EDP_Link_VSwing_List,
Help	"This feature allows for the selection of "
"Voltage Swing level for the Dock redriver DP link."

EndPage		; "DisplayPort Redriver Configuration"



#IF	($Embedded_Platform == 1)	; Embedded platform

Page "EDID-less EFP Panel DTD Timings"
Link	"Close Table" , ".."

Table	$EFP1_DTD " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters. The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage		; "EDID-less EFP Panel DTD Timings"
#ENDIF	; Embedded platform

   

EndPage		; "Device 1 (EFP1)"

Page "Device 2 (EFP2)"
Link	"Close Window" , ".."

Combo	$Int_EFP2_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
;Combo   $Int_EFP2_Type_Compat, "Select Device Type:", &Int_EFP_Device_Type_List,
Help	"This feature specifies the Device Type for this "
"add-in device."

Combo	$Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List,
Help	"This feature specifies which DVO port the device is "

Combo	$Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
Help	"This feature specifies the GPIO pin pair "
"used as DDC bus by this device.  If this device "
"doesn't support DDC bus, this field will be ignored."

Combo	$Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
Help	"This feature specifies the AUX Channel for int-DisplayPort. "
"This field is valid only if integrated DP is selected for Device Type."

 Combo	$Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_Haswell_Broadwell_LS_List,
 Help	"This feature specifies the Level shifter configuration for HDMI. "
 "This field is valid only if HDMI is selected for Device Type.\r"
 "The values applicable to Broadwell/Haswell are mentioned in the braces."
 "Select value corresponding to the platform."

#IF	($Embedded_Platform == 1)	; Embedded platform
Title	"	"

Combo	$EFP2_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
Help	"If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."

Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
#ENDIF	; Embedded platform

Title	"	"

Combo	$EFP2_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
Help	"This feature, when enabled, will set lane reversal bit for selected port "

Combo	$Int_EFP2_Port_Dockable, "Dockable", &No_Yes_List,
Help	"This feature will describe if this port is dockable or not."	
Title "Select DisplayPort Redriver "
Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration"

Page	"DisplayPort Redriver Configuration"


Combo	$Int_EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List,
Help	"This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."

Combo	$Int_EFP2_OnBoard_Pre_emphasis, "  Pre-Emphasis Level:", &DP_Link_PreEmp_List,
Help	"This feature allows for the selection of "
"Pre-Emphasis level for the OnBoard redriver DP link.\n"
		  "Level 0 (0 dB)\n"
		  "Level 1 (3.5 dB)\n"
		  "Level 2 (6.0 dB)\n"
		  "Level 3 (9.5 dB)"

Combo	$Int_EFP2_OnBoard_Voltage_Swing, "  Voltage Swing Level:", &DP_EDP_Link_VSwing_List,
Help	"This feature allows for the selection of "
"Voltage Swing level for the OnBoard Redriver DP link.\n"
		  "Swing-0 (0.4 V)\n" 
		  "Swing-1 (0.6 V)\n"
		  "Swing-2 (0.8 V)\n"


Title	"	"

Combo	$Int_EFP2_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
Help	"This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"
"Note: 5F14,078F GetMiscStatus system hook must be implemented in SBIOS and enabled in VBIOS "
"for this feature to work."


Combo	$Int_EFP2_Dock_Pre_emphasis, "  Pre-Emphasis Level:", &DP_Link_PreEmp_List,
Help	"This feature allows for the selection of "
"Pre-Emphasis level for the Dock redriver DP link."

Combo	$Int_EFP2_Dock_Voltage_Swing, "  Voltage Swing Level:", &DP_EDP_Link_VSwing_List,
Help	"This feature allows for the selection of "
"Voltage Swing level for the Dock redriver DP link."

EndPage 	; "DisplayPort Redriver Configuration"

#IF	($Embedded_Platform == 1)	; Embedded platform

Page "EDID-less EFP Panel DTD Timings"
Link	"Close Table" , ".."

Table	$EFP2_DTD " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters. The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage	;  "EDID-less EFP Panel DTD Timings"
#ENDIF	; Embedded platform


   


EndPage	; "Device 2"  (EFP2)

Page "Device 3 (EFP3)"

Link	"Close Window" , ".."

Combo	$Int_EFP3_Type, "Select Device Type:", &Int_EFP_Device_Type_List,
;Combo   $Int_EFP3_Type_Compat, "Select Device Type:", &Int_EFP_Device_Type_List,
Help	"This feature specifies the Device Type for this "
"add-in device."

Combo	$Int_EFP3_Port, "Select Output Port:", &Int_EFP_Port_List,
Help	"This feature specifies which DVO port the device is "

Combo	$Int_EFP3_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List,
Help	"This feature specifies the GPIO pin pair "
"used as DDC bus by this device.  If this device "
"doesn't support DDC bus, this field will be ignored."

Combo	$Int_EFP3_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_List,
Help	"This feature specifies the AUX Channel for int-DisplayPort. "
"This field is valid only if integrated DP is selected for Device Type."

 Combo	$Int_EFP3_HDMI_LS_Type, "Select HDMI level shifter configuration:", &Hdmi_Haswell_Broadwell_LS_List,
 Help	"This feature specifies the Level shifter configuration for HDMI. "
 "This field is valid only if HDMI is selected for Device Type.\r"
 "The values applicable to Broadwell/Haswell are mentioned in the braces."
 "Select value corresponding to the platform."


#IF	($Embedded_Platform == 1)	; Embedded platform
Title	"	"

Combo	$EFP3_EDIDless_en, "EDIDless Panel: ", &No_Yes_List,
Help	"If the Attached panel is EDIDless select Yes and the supplied DTD takes priority."

Link "EDID-less EFP Panel DTD Timings" , "EDID-less EFP Panel DTD Timings"
#ENDIF	; Embedded platform

Title	"	"

Combo	$EFP3_Lane_Reversal, "DDI Lane Reversal: ", &Disabled_Enabled_List,
Help	"This feature, when enabled, will set lane reversal bit for selected port "


Combo	$Int_EFP3_Port_Dockable, "Dockable", &No_Yes_List,
Help	"This feature will describe if this port is dockable or not."	
Title "Select DisplayPort Redriver "
Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Configuration"

Page	"DisplayPort Redriver Configuration"


Combo	$Int_EFP3_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_List,
Help	"This feature will describe if Non-dock topology/OnBoard Redriver DP Link is present or not."

Combo	$Int_EFP3_OnBoard_Pre_emphasis, "  Pre-Emphasis Level:", &DP_Link_PreEmp_List,
Help	"This feature allows for the selection of "
"Pre-Emphasis level for the OnBoard redriver DP link.\n"
		  "Level 0 (0 dB)\n"
		  "Level 1 (3.5 dB)\n"
		  "Level 2 (6.0 dB)\n"
		  "Level 3 (9.5 dB)"

Combo	$Int_EFP3_OnBoard_Voltage_Swing, "  Voltage Swing Level:", &DP_EDP_Link_VSwing_List,
Help	"This feature allows for the selection of "
"Voltage Swing level for the OnBoard redriver DP link.\n"
		  "Swing-0 (0.4 V)\n" 
		  "Swing-1 (0.6 V)\n"
		  "Swing-2 (0.8 V)\n"


Title	"	"

Combo	$Int_EFP3_Dock_Redriver_Present, "Dock Topology: (Mobile only)", &No_Yes_List,
Help	"This feature will describe if Dock Topology/Dock Redriver DP Link is present or not.\r\n\r\n"
"Note: 5F14,078F GetMiscStatus system hook must be implemented in SBIOS and enabled in VBIOS "
"for this feature to work."

Combo	$Int_EFP3_Dock_Pre_emphasis, "  Pre-Emphasis Level:", &DP_Link_PreEmp_List,
Help	"This feature allows for the selection of "
"Pre-Emphasis level for the Dock redriver DP link."

Combo	$Int_EFP3_Dock_Voltage_Swing, "  Voltage Swing Level:", &DP_EDP_Link_VSwing_List,
Help	"This feature allows for the selection of "
"Voltage Swing level for the Dock redriver DP link."

EndPage		; "DisplayPort Redriver Configuration"

#IF	($Embedded_Platform == 1)	; Embedded platform

Page "EDID-less EFP Panel DTD Timings"
Link	"Close Table" , ".."

Table	$EFP3_DTD " DTD Timings Values",
Column "Timings" , 1 byte , EHEX,
Help	"This feature allows for the definition of the DTD "
"timings parameters. The "
"table is the 18-byte DTD structure defined in the "
"VESA EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage		; "EDID-less EFP Panel DTD Timings"
#ENDIF	; Embedded platform
   


EndPage		; "Device 3  (EFP3)"
EndPage		; "Integrated DisplayPort/HDMI Configuration with External Connectors"
EndPage			; Display configuration

;==============================================================================
; Page - Display Device Toggle Lists
;------------------------------------------------------------------------------

Page "Display Device Toggle Lists (Mobile only)"

  Link "Toggle/Capabilities List 1" , "Display Toggle List 1"
  Link "Toggle/Capabilities List 2" , "Display Toggle List 2"
  Link "Toggle/Capabilities List 3" , "Display Toggle List 3"
  Link "Toggle/Capabilities List 4" , "Display Toggle List 4"

  Page "Display Toggle List 1"

    Link	"Close Table" , ".."

      Table	$Toggle_List1 "Display Toggle List 1",
      Column "Display Select", 2 bytes, EHEX,

      Help	"These toggle lists are used by the video BIOS and "
                 "Graphics drivers to help support the system BIOS with "
                 "switch display device Hot Keys.  The basic algorithm "
                 "in the current display is found on the list and the "
                 "next settable display combination is set.  If no "
                 "settable display combinations are found the function "
                 "returns fail.\r\n"
                 "\r\n"
                 "Four lists are given to allow for multiple "
                 "Hot Keys or creative solutions.\r\n"
                 "\r\n"
                 "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
                 "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tCRT\r\n"
                 "\r\n"
                 "EFPx.x nomenclature\r\n"
                 "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
                 "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
                 "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
                 "Examples:\r\n"
                 "\t Display Config\r\n"
                 "\t00000000 00000101b  ; Toggle display to EFP & CRT combination\r\n"
                 "\t00000100 00000001b  ; Toggle display to second DP Port on EFP3 and CRT combination."
  EndPage               ; Display Toggle List 1

  Page "Display Toggle List 2"

    Link	"Close Table" , ".."

      Table	$Toggle_List2 "Display Toggle List 2",
      Column    "Display Select", 2 bytes, EHEX, 

      Help	"These toggle lists are used by the video BIOS and "
                 "Graphics drivers to help support the system BIOS with "
                 "switch display device Hot Keys.  The basic algorithm "
                 "in the current display is found on the list and the "
                 "next settable display combination is set.  If no "
                 "settable display combinations are found the function "
                 "returns fail.\r\n"
                 "\r\n"
                 "Four lists are given to allow for multiple "
                 "Hot Keys or creative solutions.\r\n"
                 "\r\n"
                 "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
                 "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tCRT\r\n"
                 "\r\n"
                 "EFPx.x nomenclature\r\n"
                 "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
                 "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
                 "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
                 "Examples:\r\n"
                 "\t Display Config\r\n"
                 "\t00000000 00000101b  ; Toggle display to EFP & CRT combination\r\n"
                 "\t00000100 00000001b  ; Toggle display to second DP Port on EFP3 and CRT combination."
  EndPage               ; Display Toggle List 2

  Page "Display Toggle List 3"

    Link	"Close Table" , ".."

      Table	$Toggle_List3 "Display Toggle List 3",
      Column    "Display Select", 2 bytes, EHEX, 

      Help	"These toggle lists are used by the video BIOS and "
                 "Graphics drivers to help support the system BIOS with "
                 "switch display device Hot Keys.  The basic algorithm "
                 "in the current display is found on the list and the "
                 "next settable display combination is set.  If no "
                 "settable display combinations are found the function "
                 "returns fail.\r\n"
                 "\r\n"
                 "Four lists are given to allow for multiple "
                 "Hot Keys or creative solutions.\r\n"
                 "\r\n"
                 "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
                 "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tCRT\r\n"
                 "\r\n"
                 "EFPx.x nomenclature\r\n"
                 "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
                 "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
                 "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
                 "\r\n"
                 "Examples:\r\n"
                 "\t Display Config\r\n"
                 "\t00000000 00000101b  ; Toggle display to EFP & CRT combination\r\n"
                 "\t00000100 00000001b  ; Toggle display to second DP Port on EFP3 and CRT combination."
  EndPage               ; Display Toggle List 3

  Page "Display Toggle List 4"

    Link	"Close Table" , ".."

      Table	$Toggle_List4 "Display Toggle List 4",
      Column    "Display Select", 2 bytes, EHEX, 

      Help	"These toggle lists are used by the video BIOS and "
                 "Graphics drivers to help support the system BIOS with "
                 "switch display device Hot Keys.  The basic algorithm "
                 "in the current display is found on the list and the "
                 "next settable display combination is set.  If no "
                 "settable display combinations are found the function "
                 "returns fail.\r\n"
                 "\r\n"
                 "Four lists are given to allow for multiple "
                 "Hot Keys or creative solutions.\r\n"
                 "\r\n"
                 "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
                 "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tCRT\r\n"
                 "\r\n"
                 "EFPx.x nomenclature\r\n"
                 "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
                 "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
                 "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
                 "Examples:\r\n"
                 "\t Display Config\r\n"
                 "\t00000000 00000101b  ; Toggle display to EFP & CRT combination\r\n"
                 "\t00000100 00000001b  ; Toggle display to second DP Port on EFP3 and CRT combination."
  EndPage               ; Display Toggle List 4
EndPage                 ; Display Device Toggle Lists

;==============================================================================
; Page - Modes Removal Table
;------------------------------------------------------------------------------

Page "Modes Removal Table"

Table	$Mode_Rem_Table "Modes Removal Table",

Column "X-Resolution", 	2 bytes, DEC
Column "Y-Resolution", 	2 bytes, DEC 
Column "BPP", 		1 byte,  DEC 
Column "Refresh Rate", 	2 bytes, EHEX 
Column "Removal Flags", 1 byte,  EHEX 
Column "Panel Type", 	2 bytes, EHEX,

Help	"This feature allows removing support for selected modes "
"resolutions.\r\n"
"\r\n"
"X-Resolution, Y-Resolution, and BPP in Decimal or "
"Hexadecimal (0FFFFh or 0FFh means disable all).\r\n"
"\r\n"
"Refresh Rate bitmap selection (0 = Do not remove, 1 = "
"Remove):\r\n"
"\r\n"
"\tBit           15-14 13 12  11  10  9  8  7  6  5  4  3  2  1  0 \r\n"
"\tRRate(Hz) Reserved 25 24 50 40 30 120 100 85 75 72 70 60 56 43i \r\n"
"\r\n"
"Removal Flags bitmap selection (0 = Do not remove, 1 = "
"Remove):\r\n"
"\r\n"
"\tBit                    7               6                        5       4       3    \t   2        1        0    \r\n"
"\tComponent  Reserved  TV Scan Mode    LFP  EFP  Reserved  CRT  Driver  VBIOS \r\n"
"\r\n"
"\tNote: 1) In order to remove mode from both Windows and DOS, "
"both Bit 1 and Bit 0 must be set to 1.\r\n"
"\r\n"
"\t      2) The defaule setting '0' for Bit6 is for removing "
"Progressive scan mode from TV device, and setting '1' is for "
"removing Interlaced scan mode from TV device.\r\n"
"\r\n"
"(Mobile only) Panel Type bitmap selection (0 = Do not "
"remove, 1 = Remove if panel is active):\r\n"
"\r\n"
"\tBit  15 14 13 12 11 10  9 8 7 6 5 4 3 2 1 0 \r\n"
"\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n"
"\r\n"
"\tNote: Default is to remove a mode resolution from all "
"panel types."
EndPage

;==============================================================================
; Page - Display Configuration Removal Table
;------------------------------------------------------------------------------

Page "Display Configuration Removal Table (Mobile only)"

      Table	$Dev_Removed_Table " Display Device Configuration Removal Table",
      Column "Display Configuration" , 2 bytes , EHEX,
      
      Help	"This feature allows blocking selected display configurations "
      "by the Graphics Driver.\r\n"
      "\r\n"
      "Display Devices are specified in the following bit patterns "
      "\r\n"
      "\t15\t14\t13\t12\t11\t10\t9\t8\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n"
      "\tRsvd\tEFP3.3\tEFP2.3\tEFP1.3\tRsvd\tEFP3.2\tEFP2.2\tEFP1.2\tRsvd\tEFP2\tEFP3\tRsvd\tLFP\tEFP\tReserved\tCRT\r\n"
      "\r\n"
      "EFPx.x nomenclature\r\n"
      "EFP1.2 - 2nd daisy chained DP port on EFP1 Port\r\n"
      "EFP2.3 - 3rd daisy chained DP port on EFP2 Port\r\n"
      "EFP3.2 - 2nd daisy chained DP port on EFP3 Port\r\n"
      "Examples:\r\n"
      "\t Display Config\r\n"
      "\t00000000 00000101b  ; EFP & CRT combination to be removed\r\n"
      "\t00000100 00000001b  ; Second DP Port on EFP3 and CRT to be removed."
EndPage
;==============================================================================
; Page - OEM Customizable Modes
;------------------------------------------------------------------------------

Page "OEM Customizable Modes"

Link	"OEM Mode 1 Configuration", "OEM Mode #1"
Link	"OEM Mode 2 Configuration", "OEM Mode #2"
Link	"OEM Mode 3 Configuration", "OEM Mode #3"
Link	"OEM Mode 4 Configuration", "OEM Mode #4"
Link	"OEM Mode 5 Configuration", "OEM Mode #5"
Link	"OEM Mode 6 Configuration", "OEM Mode #6"	

Page "OEM Mode #1"

Link	"Close Table" , ".."

Title	"     8 bpp = VGA mode 60h / VESA mode 160h"
Title	"    16 bpp = VGA mode 61h / VESA mode 161h"
Title	"    32 bpp = VGA mode 62h / VESA mode 162h"

EditNum	$OEM_Mode_Flags1, "Support Flags:", BIN,
Help	"Support flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tDriver"
"\tVBIOS"
"\r\n"

EditNum	$OEM_Display_Flags1, "Display Flags:", BIN,
Help	"Display Flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\t  Bit 0"
"\r\n"
"\tLFP2"
"\tEFP2"
"\tEFP3"
"\tCRT2"
"\tLFP"
"\tEFP"
"\tReserved"
"\t  CRT"
"\r\n"

Title	"Mode Characteristics"
EditNum	$OEM_Mode_X1, "  X Resolution:", DEC,
Help	"X Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Y1, "  Y Resolution:", DEC,
Help	"Y Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Color1, "  Color Depth:", BIN,
Help	"Color Depth, bits can be set simultaneously (binary)."
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\t32 BPP"
"\t16 BPP"
"\t8 BPP"
"\r\n"

EditNum	$OEM_Mode_RRate1, "  Refresh Rate:", DEC,
Help	"Refresh rate for OEM customizable mode (decimal)."
Link "18 Bytes DTD" , "DTD"

Page "DTD"

Link	"Close Table" , ".."

Table	$OEM_Mode_DTD1 " Detailed Timings Descriptor",
Column "Timings" , 1 byte , EHEX,
Help	"This table is the 18-byte DTD(Detailed Timings"
" Descriptor) structure defined in the VESA"
" EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage             ; DTD
EndPage               ; OEM Mode #1

Page "OEM Mode #2"

Link	"Close Table" , ".."

Title	"     8 bpp = VGA mode 63h / VESA mode 163h"
Title	"    16 bpp = VGA mode 64h / VESA mode 164h"
Title	"    32 bpp = VGA mode 65h / VESA mode 165h"

EditNum	$OEM_Mode_Flags2, "Support Flags:", BIN,
Help	"Support flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tDriver"
"\tVBIOS"
"\r\n"

EditNum	$OEM_Display_Flags2, "Display Flags:", BIN,
Help	"Display Flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\t  Bit 0"
"\r\n"
"\tLFP2"
"\tEFP2"
"\tEFP3"
"\tCRT2"
"\tLFP"
"\tEFP"
"\tReserved"
"\t  CRT"
"\r\n"

Title	"Mode Characteristics"

EditNum	$OEM_Mode_X2, "  X Resolution:", DEC,
Help	"X Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Y2, "  Y Resolution:", DEC,
Help	"Y Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Color2, "  Color Depth:", BIN,
Help	"Color Depth, bits can be set simultaneously (binary)."
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\t32 BPP"
"\t16 BPP"
"\t8 BPP"
"\r\n"

EditNum	$OEM_Mode_RRate2, "  Refresh Rate:", DEC,
Help	"Refresh rate for OEM customizable mode (decimal)."

Link "18 Bytes DTD" , "DTD"

Page "DTD"

Link	"Close Table" , ".."

Table	$OEM_Mode_DTD2 " Detailed Timings Descriptor",
Column "Timings" , 1 byte , EHEX,
Help	"This table is the 18-byte DTD(Detailed Timings"
" Descriptor) structure defined in the VESA"
" EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage             ; DTD
EndPage               ; OEM Mode #2

Page "OEM Mode #3"

Link	"Close Table" , ".."

Title	"     8 bpp = VGA mode 66h / VESA mode 166h"
Title	"    16 bpp = VGA mode 67h / VESA mode 167h"
Title	"    32 bpp = VGA mode 68h / VESA mode 168h"

EditNum	$OEM_Mode_Flags3, "Support Flags:", BIN,
Help	"Support flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tDriver"
"\tVBIOS"
"\r\n"

EditNum	$OEM_Display_Flags3, "Display Flags:", BIN,
Help	"Display Flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\t  Bit 0"
"\r\n"
"\tLFP2"
"\tEFP2"
"\tEFP3"
"\tCRT2"
"\tLFP"
"\tEFP"
"\tReserved"
"\t  CRT"
"\r\n"

Title	"Mode Characteristics"

EditNum	$OEM_Mode_X3, "  X Resolution:", DEC,
Help	"X Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Y3, "  Y Resolution:", DEC,
Help	"Y Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Color3, "  Color Depth:", BIN,
Help	"Color Depth, bits can be set simultaneously (binary)."
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\t32 BPP"
"\t16 BPP"
"\t8 BPP"
"\r\n"

EditNum	$OEM_Mode_RRate3, "  Refresh Rate:", DEC,
Help	"Refresh rate for OEM customizable mode (decimal)."

Link "18 Bytes DTD" , "DTD"

Page "DTD"

Link	"Close Table" , ".."

Table	$OEM_Mode_DTD3 " Detailed Timings Descriptor",
Column "Timings" , 1 byte , EHEX,
Help	"This table is the 18-byte DTD(Detailed Timings"
" Descriptor) structure defined in the VESA"
" EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage             ; DTD
EndPage               ; OEM Mode #3

Page "OEM Mode #4"

Link	"Close Table" , ".."

Title	"     8 bpp = VGA mode 69h / VESA mode 169h"
Title	"    16 bpp = VGA mode 6Ah / VESA mode 16Ah"
Title	"    32 bpp = VGA mode 6Bh / VESA mode 16Bh"

EditNum	$OEM_Mode_Flags4, "Support Flags:", BIN,
Help	"Support flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tDriver"
"\tVBIOS"
"\r\n"

EditNum	$OEM_Display_Flags4, "Display Flags:", BIN,
Help	"Display Flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\t  Bit 0"
"\r\n"
"\tLFP2"
"\tEFP2"
"\tEFP3"
"\tCRT2"
"\tLFP"
"\tEFP"
"\tReserved"
"\t  CRT"
"\r\n"

Title	"Mode Characteristics"

EditNum	$OEM_Mode_X4, "  X Resolution:", DEC,
Help	"X Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Y4, "  Y Resolution:", DEC,
Help	"Y Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Color4, "  Color Depth:", BIN,
Help	"Color Depth, bits can be set simultaneously (binary)."
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\t32 BPP"
"\t16 BPP"
"\t8 BPP"
"\r\n"

EditNum	$OEM_Mode_RRate4, "  Refresh Rate:", DEC,
Help	"Refresh rate for OEM customizable mode (decimal)."

Link "18 Bytes DTD" , "DTD"

Page "DTD"

Link	"Close Table" , ".."

Table	$OEM_Mode_DTD4 " Detailed Timings Descriptor",
Column "Timings" , 1 byte , EHEX,
Help	"This table is the 18-byte DTD(Detailed Timings"
" Descriptor) structure defined in the VESA"
" EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage             ; DTD
EndPage               ; OEM Mode #4

Page "OEM Mode #5"

Link	"Close Table" , ".."

Title	"     8 bpp = VGA mode 6Ch / VESA mode 16Ch"
Title	"    16 bpp = VGA mode 6Dh / VESA mode 16Dh"
Title	"    32 bpp = VGA mode 6Eh / VESA mode 16Eh"

EditNum	$OEM_Mode_Flags5, "Support Flags:", BIN,
Help	"Support flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tDriver"
"\tVBIOS"
"\r\n"

EditNum	$OEM_Display_Flags5, "Display Flags:", BIN,
Help	"Display Flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\t  Bit 0"
"\r\n"
"\tLFP2"
"\tEFP2"
"\tEFP3"
"\tCRT2"
"\tLFP"
"\tEFP"
"\tReserved"
"\t  CRT"
"\r\n"

Title	"Mode Characteristics"

EditNum	$OEM_Mode_X5, "  X Resolution:", DEC,
Help	"X Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Y5, "  Y Resolution:", DEC,
Help	"Y Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Color5, "  Color Depth:", BIN,
Help	"Color Depth, bits can be set simultaneously (binary)."
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\t32 BPP"
"\t16 BPP"
"\t8 BPP"
"\r\n"

EditNum	$OEM_Mode_RRate5, "  Refresh Rate:", DEC,
Help	"Refresh rate for OEM customizable mode (decimal)."

Link "18 Bytes DTD" , "DTD"

Page "DTD"

Link	"Close Table" , ".."

Table	$OEM_Mode_DTD5 " Detailed Timings Descriptor",
Column "Timings" , 1 byte , EHEX,
Help	"This table is the 18-byte DTD(Detailed Timings"
" Descriptor) structure defined in the VESA"
" EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage              ; DTD
EndPage                ; OEM Mode #5

Page "OEM Mode #6"

Link	"Close Table" , ".."

Title	"     8 bpp = VGA mode 6Fh / VESA mode 16Fh"
Title	"    16 bpp = VGA mode 70h / VESA mode 170h"
Title	"    32 bpp = VGA mode 71h / VESA mode 171h"

EditNum	$OEM_Mode_Flags6, "Support Flags:", BIN,
Help	"Support flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tDriver"
"\tVBIOS"
"\r\n"

EditNum	$OEM_Display_Flags6, "Display Flags:", BIN,
Help	"Display Flags:"
"(0 = Disabled, 1 = Enabled)"
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\t  Bit 0"
"\r\n"
"\tLFP2"
"\tEFP2"
"\tEFP3"
"\tCRT2"
"\tLFP"
"\tEFP"
"\tReserved"
"\t  CRT"
"\r\n"

Title	"Mode Characteristics"

EditNum	$OEM_Mode_X6, "  X Resolution:", DEC,
Help	"X Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Y6, "  Y Resolution:", DEC,
Help	"Y Resolution in pixels (decimal)."

EditNum	$OEM_Mode_Color6, "  Color Depth:", BIN,
Help	"Color Depth, bits can be set simultaneously (binary)."
"\r\n\r\n"
"\tBit 7"
"\tBit 6"
"\tBit 5"
"\tBit 4"
"\tBit 3"
"\tBit 2"
"\tBit 1"
"\tBit 0"
"\r\n"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\tRsvd"
"\t32 BPP"
"\t16 BPP"
"\t8 BPP"
"\r\n"

EditNum	$OEM_Mode_RRate6, "  Refresh Rate:", DEC,
Help	"Refresh rate for OEM customizable mode (decimal)."

Link "18 Bytes DTD" , "DTD"

Page "DTD"

Link	"Close Table" , ".."

Table	$OEM_Mode_DTD6 " Detailed Timings Descriptor",
Column "Timings" , 1 byte , EHEX,
Help	"This table is the 18-byte DTD(Detailed Timings"
" Descriptor) structure defined in the VESA"
" EDID version 1.x.\r\n"  
"\r\n"
"\tByte1 \t: Low Byte of DClk in 10 KHz\r\n"
"\tByte2 \t: High Byte of DClk in 10 KHz\r\n"
"\tByte3 \t: Horizontal Active in pixels, LSB\r\n"
"\tByte4 \t: Horizontal Blanking in pixels, LSB\r\n"
"\tByte5 \t: Bit 7-4: Upper 4 bits of Hor. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\tByte6 \t: Vertical Active in lines, LSB\r\n"
"\tByte7 \t: Vertical Blanking in lines, LSB\r\n"
"\tByte8 \t: Bit 7-4: Upper 4 bits of Vert. Active\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\tByte9  \t: HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\tByte10 \t: HSync Pulse Width in pixels, LSB\r\n"
"\tByte11 \t: Bit 7-4: Lower 4 bits of VSync Offset\r\n"
"\t   \t: Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\tByte12 \t: Bit 7-6: Upper 2 bits of HSync Offset\r\n"
"\t   \t: Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
"\t   \t: Bit 3-2: Upper 2 bits of VSync Offset\r\n"
"\t   \t: Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\tByte13 \t: Horizontal Image Size, LSB\r\n"
"\tByte14 \t: Vertical Image Size, LSB\r\n"
"\tByte15 \t: Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
"\t   \t: Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\tByte16 \t: Horizontal Border in pixels\r\n"
"\tByte17 \t: Vertical Border in lines\r\n"
"\tByte18 \t: Flags:\r\n"
"\t   \t:   Bit 7:   0 = Non-interlaced, 1 = Interlaced\r\n"
"\t   \t:   Bit 6-5: 00 = Reserved\r\n"
"\t   \t:   Bit 4-3: 11 = Digital Separate\r\n"
"\t   \t:   Bit 2:   Vertical Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 1:   Horizontal Polarity (0 = Negative, 1 = Positive)\r\n"
"\t   \t:   Bit 0:   0 = Reserved"
EndPage            ; DTD
EndPage                ; OEM Mode #6
EndPage                   ; OEM Customizable Modes

#IF 0
;==============================================================================
; Page - Test Page (Debug only)
;------------------------------------------------------------------------------

Page "Test Page (Debug only)"

  ;	Title	"|------------- Maximum Length of revision note. --------------------|"

Title	" Note:  This page is for test purposes only."
Title	" Default values should not be changed for released software."

Combo	$SV_Dis_Arbiter, "  Disable VGA Fast Arbiter: ", &No_Yes_List,
Help	"If select Yes, the VGA Fast Arbiter is Disabled for the following "
"combinations: \r\n"
"1) FSB533/DDR266 \r\n"
"2) FSB400/DDR266 \r\n"
"3) FSB533/DDR200 \r\n"
"\r\n"
"If selec No, the VGA Fast Arbiter is always enabled"

Combo	$SV_Setmode_No_DVO, "  Setmode without Update DVO timings: ", &No_Yes_List,
Help	"If select Yes, VBIOS setmode will skip DVO update.\r\n"
"If select No, VBIOS setmode will update DVO timings"

Combo	$SV_Wait_Timeout_Hang, "  Allow Wait VBlank Timeout Hang: ", &No_Yes_List,
Help	"If select Yes, VBIOS will allow software hang when Wait VBlank is timed out."

Combo	$RelStage, "  VBIOS Release Stage:", &RelStage,
Help	"This is the stage of the video BIOS Release.   Selecting "
"'Evaluation' will cause an evaluation message to be "
"displayed with the signon messages.\r\n"
"\r\n"
"Evaluation allows AIM modules to be included for testing, "
"but forces a 10 second POST delay to assure it is not "
"shipped in evaluation mode.\r\n"
"\r\n"
"Production means OEMs can use it for production and there "
"won't be a forced evaluation message or delay of 10 second "
"during boot."

Title "Register Tables "
Link "MMIO Register Boot Table" , "MMIO Boot Registers"
Link "I/O SW Flag Register Table" , "I/O SW Flag Registers"
Link "MMIO SW Flag Register Table" , "MMIO SW Flag Registers"

Page "MMIO Boot Registers"

Link	"Close Table" , ".."

Table	$MMIO_Boot_Table "MMIO Registers",
Column "Address", 4 bytes, EHEX
Column "Data", 4 bytes, EHEX, 
Help	"This is a memory mapped I/O register boot table.  "
"This table is loaded during video BIOS POST.  The "
"data as well as the address are double words." 
EndPage

Page "I/O SW Flag Registers"

Link	"Close Table" , ".."

Table	$SWF_IO_Table "I/O Software flag Registers",
Column "Address", 1 bytes, EHEX
Column "Data", 1 bytes, EHEX, 
Help	"This is a I/O software flag boot table.  This "
"table is loaded during video BIOS POST.  The data "
"as well as the address are bytes." 
EndPage

Page "MMIO SW Flag Registers"

Link	"Close Table" , ".."

Table	$SWF_MMIO_Table "MMIO Software flag Registers",
Column "Address", 4 bytes, EHEX
Column "Data", 4 bytes, EHEX, 
Help	"This is a MMIO software flag boot table.  This "
"table is loaded during video BIOS POST.  The data "
"as well as the address are DWORDs." 
EndPage
EndPage

;============================================================================
; End of File
;------------------------------------------------------------------------------
  
#ENDIF